lspci/
capability.rs

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1// Copyright 2020 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4use crate::util::is_set;
5use bitfield::bitfield;
6use fidl_fuchsia_hardware_pci::Capability as FidlCapability;
7use std::fmt;
8use zerocopy::{FromBytes, Immutable, IntoBytes, KnownLayout, Ref};
9
10// Capability types are documented in PCI Local Bus Specification v3.0 Appendix H
11enum CapabilityType {
12    Null,
13    PciPowerManagement,
14    Agp,
15    VitalProductData,
16    SlotIdentification,
17    Msi,
18    CompactPciHotSwap,
19    PciX,
20    HyperTransport,
21    Vendor,
22    DebugPort,
23    CompactPciCrc,
24    PciHotplug,
25    PciBridgeSubsystemVendorId,
26    Agp8x,
27    SecureDevice,
28    PciExpress,
29    MsiX,
30    SataDataNdxCfg,
31    AdvancedFeatures,
32    EnhancedAllocation,
33    FlatteningPortalBridge,
34    Unknown(u8),
35}
36
37impl From<u8> for CapabilityType {
38    fn from(value: u8) -> Self {
39        match value {
40            0x00 => CapabilityType::Null,
41            0x01 => CapabilityType::PciPowerManagement,
42            0x02 => CapabilityType::Agp,
43            0x03 => CapabilityType::VitalProductData,
44            0x04 => CapabilityType::SlotIdentification,
45            0x05 => CapabilityType::Msi,
46            0x06 => CapabilityType::CompactPciHotSwap,
47            0x07 => CapabilityType::PciX,
48            0x08 => CapabilityType::HyperTransport,
49            0x09 => CapabilityType::Vendor,
50            0x0a => CapabilityType::DebugPort,
51            0x0b => CapabilityType::CompactPciCrc,
52            0x0c => CapabilityType::PciHotplug,
53            0x0d => CapabilityType::PciBridgeSubsystemVendorId,
54            0x0e => CapabilityType::Agp8x,
55            0x0f => CapabilityType::SecureDevice,
56            0x10 => CapabilityType::PciExpress,
57            0x11 => CapabilityType::MsiX,
58            0x12 => CapabilityType::SataDataNdxCfg,
59            0x13 => CapabilityType::AdvancedFeatures,
60            0x14 => CapabilityType::EnhancedAllocation,
61            0x15 => CapabilityType::FlatteningPortalBridge,
62            _ => CapabilityType::Unknown(value),
63        }
64    }
65}
66
67pub struct Capability<'a> {
68    offset: usize,
69    config: &'a [u8],
70    cap_type: CapabilityType,
71}
72
73impl<'a> fmt::Display for Capability<'a> {
74    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
75        write!(f, "Capabilities: [{:#2x}] ", self.offset)?;
76        match self.cap_type {
77            CapabilityType::Null => write!(f, "Null"),
78            CapabilityType::PciPowerManagement => write!(f, "PCI Power Management"),
79            CapabilityType::Agp => write!(f, "AGP"),
80            CapabilityType::VitalProductData => write!(f, "Vital Product Data"),
81            CapabilityType::SlotIdentification => write!(f, "Slot Identification"),
82            CapabilityType::Msi => self.msi(f),
83            CapabilityType::CompactPciHotSwap => write!(f, "CompactPCI Hotswap"),
84            CapabilityType::PciX => write!(f, "PCI-X"),
85            CapabilityType::HyperTransport => write!(f, "HyperTransport"),
86            CapabilityType::Vendor => self.vendor(f),
87            CapabilityType::DebugPort => write!(f, "Debug Port"),
88            CapabilityType::CompactPciCrc => write!(f, "CompactPCI CRC"),
89            CapabilityType::PciHotplug => write!(f, "PCI Hotplug"),
90            CapabilityType::PciBridgeSubsystemVendorId => write!(f, "PCI Bridge Subsystem VID"),
91            CapabilityType::Agp8x => write!(f, "AGP 8x"),
92            CapabilityType::SecureDevice => write!(f, "Secure Device"),
93            CapabilityType::PciExpress => self.pci_express(f),
94            CapabilityType::MsiX => self.msi_x(f),
95            CapabilityType::SataDataNdxCfg => write!(f, "SATA Data Ndx Config"),
96            CapabilityType::AdvancedFeatures => write!(f, "Advanced Features"),
97            CapabilityType::EnhancedAllocation => write!(f, "Enhanced Allocations"),
98            CapabilityType::FlatteningPortalBridge => write!(f, "Flattening Portal Bridge"),
99            CapabilityType::Unknown(id) => write!(f, "Unknown Capability (id = {:#2x})", id),
100        }
101    }
102}
103
104impl<'a> Capability<'a> {
105    pub fn new(capability: &'a FidlCapability, config: &'a [u8]) -> Self {
106        Capability {
107            offset: capability.offset as usize,
108            config,
109            cap_type: CapabilityType::from(capability.id),
110        }
111    }
112
113    fn msi(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
114        // MSI: Enable+ Count=1/1 Maskable- 64bit+
115        // Address: 00000000fee00698  Data: 0000
116        let control = MsiControl(
117            ((self.config[self.offset + 3] as u16) << 8) | self.config[self.offset + 2] as u16,
118        );
119        write!(
120            f,
121            "MSI: Enable{} Count={}/{} Maskable{} 64bit{}\n",
122            is_set(control.enable()),
123            msi_mms_to_value(control.mms_enabled()),
124            msi_mms_to_value(control.mms_capable()),
125            is_set(control.pvm_capable()),
126            is_set(control.can_be_64bit())
127        )?;
128
129        if control.can_be_64bit() {
130            let (msi, _) = Ref::<_, Msi64Capability>::from_prefix(
131                &self.config[self.offset..self.config.len()],
132            )
133            .unwrap();
134            write!(
135                f,
136                "\t\tAddress: {:#010x} {:#08x} Data: {:#06x}",
137                { msi.address_upper },
138                { msi.address },
139                { msi.data }
140            )
141        } else {
142            let (msi, _) = Ref::<_, Msi32Capability>::from_prefix(
143                &self.config[self.offset..self.config.len()],
144            )
145            .unwrap();
146            write!(f, "\t\tAddress: {:#010x} Data: {:#06x}", { msi.address }, { msi.data })
147        }
148    }
149
150    fn msi_x(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
151        let (msix, _) =
152            Ref::<_, MsixCapability>::from_prefix(&self.config[self.offset..self.config.len()])
153                .unwrap();
154        let control = MsixControl(msix.control);
155        let table = MsixBarField(msix.table);
156        let pba = MsixBarField(msix.pba);
157        write!(
158            f,
159            "MSI-X: Enable{} Count={} Masked{} TBIR={} TOff={:#x} PBIR={} POff={:#x}",
160            is_set(control.enable()),
161            control.table_size() + 1,
162            is_set(control.function_mask()),
163            table.bir(),
164            table.offset() << 3,
165            pba.bir(),
166            pba.offset() << 3,
167        )
168    }
169
170    fn pci_express(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
171        let (pcie, _) = Ref::<_, PciExpressCapability>::from_prefix(
172            &self.config[self.offset..self.config.len()],
173        )
174        .unwrap();
175        // PCIe Base Specification v4 section 7.5.3
176        let pcie_capabilities = PcieCapabilitiesField(pcie.pcie_capabilities);
177        let dev_type = PcieDevicePortType::from(pcie_capabilities.device_type());
178        let slot = match dev_type {
179            PcieDevicePortType::PCIEEP
180            | PcieDevicePortType::LPCIEEP
181            | PcieDevicePortType::RCIEP
182            | PcieDevicePortType::RCEC => String::from(""),
183            _ => format!(" (Slot{})", is_set(pcie_capabilities.slot_implemented())),
184        };
185        write!(
186            f,
187            "Express (v{}) {}{}, MSI {:#02x}",
188            pcie_capabilities.version(),
189            dev_type,
190            slot,
191            pcie_capabilities.irq_number()
192        )
193    }
194
195    fn vendor(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
196        write!(f, "Vendor Specific Information: Len={:#2x}", self.config[self.offset + 2])
197    }
198}
199
200fn msi_mms_to_value(mms: u16) -> u8 {
201    match mms {
202        0x000 => 1,
203        0x001 => 2,
204        0x010 => 4,
205        0x011 => 8,
206        0x100 => 16,
207        0x101 => 32,
208        _ => 0,
209    }
210}
211
212bitfield! {
213    struct MsiControl(u16);
214    enable, _: 0;
215    mms_capable, _: 3, 1;
216    mms_enabled, _: 6, 4;
217    can_be_64bit, _: 7;
218    pvm_capable, _: 8;
219    _reserved, _: 15, 9;
220}
221
222#[derive(IntoBytes, KnownLayout, FromBytes, Immutable)]
223#[repr(C, packed)]
224struct Msi32Capability {
225    id: u8,
226    next: u8,
227    control: u16,
228    address: u32,
229    data: u16,
230}
231
232#[derive(IntoBytes, KnownLayout, FromBytes, Immutable)]
233#[repr(C, packed)]
234struct Msi64Capability {
235    id: u8,
236    next: u8,
237    control: u16,
238    address: u32,
239    address_upper: u32,
240    data: u16,
241}
242
243#[derive(IntoBytes, KnownLayout, FromBytes, Immutable)]
244#[repr(C, packed)]
245struct MsixCapability {
246    id: u8,
247    next: u8,
248    control: u16,
249    table: u32,
250    pba: u32,
251}
252
253bitfield! {
254    pub struct MsixControl(u16);
255    table_size, _: 10, 0;
256    _reserved, _: 13, 11;
257    function_mask, _: 14;
258    enable, _: 15;
259}
260
261bitfield! {
262    pub struct MsixBarField(u32);
263    bir, _: 2, 0;
264    offset, _: 31, 3;
265}
266
267bitfield! {
268    pub struct PcieCapabilitiesField(u16);
269    version, _: 3, 0;
270    device_type, _: 7, 4;
271    slot_implemented, _: 8;
272    irq_number, _: 13, 9;
273    _reserved, _: 15, 14;
274}
275
276// PCIe Base Specification Table 7-17: PCI Express Capabilities Register
277enum PcieDevicePortType {
278    PCIEEP,
279    LPCIEEP,
280    RCIEP,
281    RCEC,
282    RPPCIERC,
283    UPPCIES,
284    DPPCIES,
285    PCIE2PCIB,
286    PCI2PCIEB,
287    Unknown(u16),
288}
289
290impl From<u16> for PcieDevicePortType {
291    fn from(value: u16) -> Self {
292        match value {
293            0b0000 => PcieDevicePortType::PCIEEP,
294            0b0001 => PcieDevicePortType::LPCIEEP,
295            0b1001 => PcieDevicePortType::RCIEP,
296            0b1010 => PcieDevicePortType::RCEC,
297            0b0100 => PcieDevicePortType::RPPCIERC,
298            0b0101 => PcieDevicePortType::UPPCIES,
299            0b0110 => PcieDevicePortType::DPPCIES,
300            0b0111 => PcieDevicePortType::PCIE2PCIB,
301            0b1000 => PcieDevicePortType::PCI2PCIEB,
302            _ => PcieDevicePortType::Unknown(value),
303        }
304    }
305}
306
307impl fmt::Display for PcieDevicePortType {
308    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
309        write!(
310            f,
311            "{}",
312            match self {
313                PcieDevicePortType::PCIEEP => "PCI Express Endpoint",
314                PcieDevicePortType::LPCIEEP => "Legacy PCI Express Endpoint",
315                PcieDevicePortType::RCIEP => "Root Complex Integrated Endpoint",
316                PcieDevicePortType::RCEC => "Root Complex Event Collector",
317                PcieDevicePortType::RPPCIERC => "Root Port of PCI Express Root Complex",
318                PcieDevicePortType::UPPCIES => "Upstream Port of PCI Express Switch",
319                PcieDevicePortType::DPPCIES => "Downstream Port of PCI Express Switch",
320                PcieDevicePortType::PCIE2PCIB => "PCI Express to PCI/PCI-X Bridge",
321                PcieDevicePortType::PCI2PCIEB => "PCI/PCI-X to PCI Express Bridge",
322                PcieDevicePortType::Unknown(x) => return write!(f, "Unknown PCIe Type ({:#x})", x),
323            }
324        )
325    }
326}
327
328#[derive(IntoBytes, KnownLayout, FromBytes, Immutable)]
329#[repr(C, packed)]
330struct PciExpressCapability {
331    id: u8,
332    next: u8,
333    pcie_capabilities: u16,
334    device_capabilities: u32,
335    device_control: u16,
336    device_status: u16,
337}
lspci/capability.rs

lspci/
capability.rs
