fidl_data_zbi/
driver_config.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use bitflags::bitflags;
11use zerocopy::{FromBytes, IntoBytes};
12
13/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
14#[repr(u32)]
15#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
16pub enum KernelDriver {
17    /// 'PSCI'
18    ArmPsci = 0x49435350,
19
20    /// 'PSCS'
21    ArmPsciCpuSuspend = 0x53435350,
22
23    /// 'GIC2'
24    ArmGicV2 = 0x32434947,
25
26    /// 'GIC3'
27    ArmGicV3 = 0x33434947,
28
29    /// 'ATIM'
30    ArmGenericTimer = 0x4d495441,
31
32    /// 'ATMM'
33    ArmGenericTimerMmio = 0x4d4d5441,
34
35    /// 'PL0U'
36    Pl011Uart = 0x55304c50,
37
38    /// 'AMLU'
39    AmlogicUart = 0x554c4d41,
40
41    /// 'AMLH'
42    AmlogicHdcp = 0x484c4d41,
43
44    /// 'DW8U'
45    Dw8250Uart = 0x44573855,
46
47    /// 'RMLH' (typoed, originally intended to by 'AMLR')
48    AmlogicRngV1 = 0x484c4d52,
49
50    /// 'AMLR'
51    AmlogicRngV2 = 0x524c4d41,
52
53    /// 'WD32'
54    Generic32Watchdog = 0x32334457,
55
56    /// 'GENI'
57    GeniUart = 0x494E4547,
58
59    /// '8250'
60    I8250PioUart = 0x30353238,
61
62    /// '825M'
63    I8250Mmio32Uart = 0x4d353238,
64
65    /// '825B'
66    I8250Mmio8Uart = 0x42353238,
67
68    /// 'MMTP'
69    MotmotPower = 0x4d4d5450,
70
71    /// '370P'
72    As370Power = 0x50303733,
73
74    /// 'MNFP'
75    MoonflowerPower = 0x4d4e4650,
76
77    /// 'IRSP'
78    IrisPower = 0x49525350,
79
80    /// 'IMXU'
81    ImxUart = 0x55584d49,
82
83    /// 'PLIC'
84    RiscvPlic = 0x43494C50,
85
86    /// 'RTIM'
87    RiscvGenericTimer = 0x4D495452,
88
89    /// 'PXAU'
90    PxaUart = 0x50584155,
91
92    /// 'EXYU'
93    ExynosUsiUart = 0x45585955,
94
95    /// `QRNG`
96    QcomRng = 0x474E5251,
97
98    /// 'SMMU'
99    ArmSmmu = 0x554D4D51,
100}
101
102impl KernelDriver {
103    pub fn from_raw(raw: u32) -> Option<Self> {
104        match raw {
105            0x49435350 => Some(Self::ArmPsci),
106
107            0x53435350 => Some(Self::ArmPsciCpuSuspend),
108
109            0x32434947 => Some(Self::ArmGicV2),
110
111            0x33434947 => Some(Self::ArmGicV3),
112
113            0x4d495441 => Some(Self::ArmGenericTimer),
114
115            0x4d4d5441 => Some(Self::ArmGenericTimerMmio),
116
117            0x55304c50 => Some(Self::Pl011Uart),
118
119            0x554c4d41 => Some(Self::AmlogicUart),
120
121            0x484c4d41 => Some(Self::AmlogicHdcp),
122
123            0x44573855 => Some(Self::Dw8250Uart),
124
125            0x484c4d52 => Some(Self::AmlogicRngV1),
126
127            0x524c4d41 => Some(Self::AmlogicRngV2),
128
129            0x32334457 => Some(Self::Generic32Watchdog),
130
131            0x494E4547 => Some(Self::GeniUart),
132
133            0x30353238 => Some(Self::I8250PioUart),
134
135            0x4d353238 => Some(Self::I8250Mmio32Uart),
136
137            0x42353238 => Some(Self::I8250Mmio8Uart),
138
139            0x4d4d5450 => Some(Self::MotmotPower),
140
141            0x50303733 => Some(Self::As370Power),
142
143            0x4d4e4650 => Some(Self::MoonflowerPower),
144
145            0x49525350 => Some(Self::IrisPower),
146
147            0x55584d49 => Some(Self::ImxUart),
148
149            0x43494C50 => Some(Self::RiscvPlic),
150
151            0x4D495452 => Some(Self::RiscvGenericTimer),
152
153            0x50584155 => Some(Self::PxaUart),
154
155            0x45585955 => Some(Self::ExynosUsiUart),
156
157            0x474E5251 => Some(Self::QcomRng),
158
159            0x554D4D51 => Some(Self::ArmSmmu),
160
161            _ => None,
162        }
163    }
164}
165
166/// Kernel driver struct that can be used for simple drivers.
167/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
168/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
169#[repr(C)]
170#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
171pub struct DcfgSimple {
172    pub mmio_phys: u64,
173    pub irq: u32,
174    pub flags: u32,
175}
176
177#[repr(C)]
178#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
179pub struct KernelDriverIrqFlags(u32);
180
181bitflags::bitflags! {
182    impl KernelDriverIrqFlags : u32 {
183
184        /// When no flag is set, implies no information was obtained, and the
185        /// kernel will apply default configuration as it sees fit.
186        const EDGE_TRIGGERED = 1 << 0;
187        const LEVEL_TRIGGERED = 1 << 1;
188
189        /// Interpretation depends on whether is edge or level triggered.
190        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
191        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
192        const POLARITY_LOW = 1 << 2;
193
194        /// Interpretation depends on whether is edge or level triggered.
195        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
196        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
197        const POLARITY_HIGH = 1 << 3;
198  }
199}
200
201/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
202#[repr(C)]
203#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
204pub struct DcfgSimplePio {
205    pub base: u16,
206    pub reserved: u16,
207    pub irq: u32,
208}
209
210/// for ZBI_KERNEL_DRIVER_ARM_PSCI
211#[repr(C)]
212#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
213pub struct DcfgArmPsciDriver {
214    pub use_hvc: u8,
215    pub reserved: [u8; 7],
216    pub shutdown_args: [u64; 3],
217    pub reboot_args: [u64; 3],
218    pub reboot_bootloader_args: [u64; 3],
219    pub reboot_recovery_args: [u64; 3],
220}
221
222/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
223#[repr(C)]
224#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
225pub struct DcfgArmGicV2Driver {
226    pub mmio_phys: u64,
227    pub msi_frame_phys: u64,
228    pub gicd_offset: u64,
229    pub gicc_offset: u64,
230    pub gich_offset: u64,
231    pub gicv_offset: u64,
232    pub ipi_base: u32,
233    pub optional: u8,
234    pub use_msi: u8,
235    pub reserved: u16,
236}
237
238/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
239#[repr(C)]
240#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
241pub struct DcfgArmGicV3Driver {
242    pub mmio_phys: u64,
243    pub gicd_offset: u64,
244    pub gicr_offset: u64,
245    pub gicr_stride: u64,
246    pub reserved0: u64,
247    pub ipi_base: u32,
248    pub optional: u8,
249    pub reserved1: [u8; 3],
250}
251
252/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
253#[repr(C)]
254#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
255pub struct DcfgArmGenericTimerDriver {
256    pub irq_phys: u32,
257    pub irq_virt: u32,
258    pub irq_sphys: u32,
259    pub freq_override: u32,
260}
261
262#[repr(C)]
263#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
264pub struct DcfgArmGenericTimerMmioFrame {
265    /// Base address for the frame's EL1 view.
266    pub mmio_phys_el1: u64,
267
268    /// Base address for the frame's EL0 view.
269    /// This is optional.
270    pub mmio_phys_el0: u64,
271
272    /// IRQ information for physical timer. This is mandatory.
273    pub irq_phys: u32,
274
275    /// Same scheme as `DcfgSimple::irq`. This is mandatory.
276    pub irq_phys_flags: u32,
277
278    /// IRQ information for virtual timer.
279    /// This is optional.
280    /// When is not present both `irq_virt` and `irq_virt_flags` will be zero.
281    pub irq_virt: u32,
282
283    /// Same scheme as `DcfgSimple::irq`.
284    pub irq_virt_flags: u32,
285}
286
287/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER_MMIO
288#[repr(C)]
289#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
290pub struct DcfgArmGenericTimerMmioDriver {
291    /// Base address of `CNTCTLBase` frame.
292    pub mmio_phys: u64,
293
294    /// The frequency of the main counter for the timer.
295    pub frequency: u32,
296
297    /// Bitmask containing the set of active frames.
298    /// The `i-th` frame is considered active iff the `i`-th bit is set.
299    /// Note: While there may be up to 8 frames, both missing and disabled frames are treated
300    /// as inactive. Disabled frame information will be present, while missing frames will be zeroed.
301    pub active_frames_mask: u8,
302    pub reserved0: [u8; 3],
303
304    /// Information for each individual frame.
305    /// Inactive frames must be zero-filled.
306    pub frames: [DcfgArmGenericTimerMmioFrame; 8],
307}
308
309/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
310#[repr(C)]
311#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
312pub struct DcfgAmlogicHdcpDriver {
313    pub preset_phys: u64,
314    pub hiu_phys: u64,
315    pub hdmitx_phys: u64,
316}
317
318/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V1
319/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V2
320#[repr(C)]
321#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
322pub struct DcfgAmlogicRngDriver {
323    pub rng_data_phys: u64,
324    pub rng_status_phys: u64,
325    pub rng_refresh_interval_usec: u64,
326}
327
328/// Defines a register write action for a generic kernel watchdog driver.  An
329/// action consists of the following steps.
330///
331/// 1) Read from the register located a physical address |addr|
332/// 2) Clear all of the bits in the value which was read using the |clr_mask|
333/// 3) Set all of the bits in the value using the |set_mask|
334/// 4) Write this value back to the address located at addr
335#[repr(C)]
336#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
337pub struct DcfgGeneric32WatchdogAction {
338    pub addr: u64,
339    pub clr_mask: u32,
340    pub set_mask: u32,
341}
342
343#[repr(C)]
344#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
345pub struct KernelDriverGeneric32WatchdogFlags(u32);
346
347bitflags::bitflags! {
348    impl KernelDriverGeneric32WatchdogFlags : u32 {
349        const ENABLED = 1 << 0;
350  }
351}
352
353/// 1ms
354pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;
355
356/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
357/// kernel driver which may be passed by a bootloader.  Field definitions are as
358/// follows.
359#[repr(C)]
360#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
361pub struct DcfgGeneric32Watchdog {
362    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
363    pub pet_action: DcfgGeneric32WatchdogAction,
364
365    /// The address and masks needed to enable a hardware watchdog timer.  If enable
366    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
367    pub enable_action: DcfgGeneric32WatchdogAction,
368
369    /// The address and masks needed to disable a hardware watchdog timer.  If
370    /// disable is an unsupported operation, the addr of the |disable_action| shall
371    /// be zero.
372    pub disable_action: DcfgGeneric32WatchdogAction,
373
374    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
375    /// watchdog timer driver must pet the watch dog at least this often.  The value
376    /// must be at least 1 mSec, typically much larger (on the order of a second or
377    /// two).
378    pub watchdog_period_nsec: i64,
379
380    /// Storage for additional flags.  Currently, only one flag is defined,
381    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
382    /// was left enabled by the bootloader at startup.
383    pub flags: KernelDriverGeneric32WatchdogFlags,
384    pub reserved: u32,
385}
386
387/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
388#[repr(C)]
389#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
390pub struct DcfgRiscvPlicDriver {
391    /// Physical address of the PLIC MMIO region.
392    pub mmio_phys: u64,
393
394    /// Size in bytes of the PLIC MMIO region.
395    pub size_bytes: u32,
396
397    /// Number of supported IRQs.
398    pub num_irqs: u32,
399}
400
401/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
402#[repr(C)]
403#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
404pub struct DcfgRiscvGenericTimerDriver {
405    pub freq_hz: u32,
406    pub reserved: u32,
407}
408
409#[repr(C)]
410#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
411pub struct ArmPsciCpuSuspendStateFlags(u32);
412
413bitflags::bitflags! {
414    impl ArmPsciCpuSuspendStateFlags : u32 {
415
416        /// If set, when entering the associated low power state the CPU's architectural timer will be
417        /// turned off, making it an unsuitable source for exiting the low power state.
418        /// A different source must be programmed.
419        const LOCAL_TIMER_STOPS = 1 << 0;
420
421        /// If set, the PSCI CPU Suspend operation will affect the entire power domain, implying all other
422        /// CPUs of the power domain must be in a low power mode. That is, the last CPU in the power
423        /// domain is the one to enter this power state.
424        const TARGETS_POWER_DOMAIN = 1 << 1;
425  }
426}
427
428/// The ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND's payload consists on any number of
429/// `DcfgArmPsciCpuSuspendState` entries.
430///
431/// The length of the item is `sizeof(zbi_dcfg_arm_psci_cou_suspend_state_t)` times the number of
432/// entries. Each entry describes an 'idle state' that can be entered through PSCI CPU Suspend call.
433///
434/// Entries in the table may be in any order, and only a single item of type
435/// ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND should be present in the ZBI.
436#[repr(C)]
437#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
438pub struct DcfgArmPsciCpuSuspendState {
439    /// Unique identifier representing this suspend state.
440    pub id: u32,
441
442    /// PSCI power_state as described in "Section 5.4.2. of Arm Power State Coordination Interface"
443    /// v1.3.
444    pub power_state: u32,
445    pub flags: ArmPsciCpuSuspendStateFlags,
446
447    /// Latency in microseconds to enter the low power state.
448    pub entry_latency_us: u32,
449
450    /// Latency in microseconds to exit the low power state.
451    pub exit_latency_us: u32,
452
453    /// Minimum time in microseconds, including `entry_latency`, to stay in this low power state.
454    /// Spending less time would be inefficient energy-wise.
455    pub min_residency_us: u32,
456}
457
458#[repr(C)]
459#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
460pub struct QcomRngFlags(u32);
461
462bitflags::bitflags! {
463    impl QcomRngFlags : u32 {
464
465        /// The driver has been handed off, configured and initialized.
466        const ENABLED = 1 << 0;
467  }
468}
469
470#[repr(C)]
471#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
472pub struct DcfgQcomRng {
473    /// Base address of the register banks for the device.
474    pub mmio_phys: u64,
475    pub flags: QcomRngFlags,
476    pub reserved: [u8; 4],
477}
478
479pub const KERNEL_DRIVER_SMMU_MAX_IRQS: u32 = 128;
480
481pub const KERNEL_DRIVER_SMMU_MAX_HANDOFF_SMRS: u32 = 16;
482
483/// The IRQ flags as they would be reported by a device tree description.
484#[repr(C)]
485#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
486pub struct ArmSmmuIrqFlags(u32);
487
488bitflags::bitflags! {
489    impl ArmSmmuIrqFlags : u32 {
490
491        /// A rising edge triggered interrupt.
492        const RISING_EDGE = 1 << 0;
493
494        /// A falling edge triggered interrupt.
495        const FALLING_EDGE = 1 << 1;
496
497        /// An active high level triggered interrupt.
498        const ACTIVE_HIGH = 1 << 2;
499
500        /// An active low level triggered interrupt.
501        const ACTIVE_LOW = 1 << 3;
502  }
503}
504
505#[repr(C)]
506#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
507pub struct DcfgArmSmmuIrq {
508    /// The IRQ number reported as an "absolute" GIC interrupt index.  SMMU
509    /// interrupts are expected to be SPIs, and the SPI range of a GIC's
510    /// interrupt indices starts at 32.  Because of this, it can be assumed that
511    /// any interrupt number which is < 32 indicates an invalid interrupt.
512    pub num: u32,
513
514    /// The IRQ flags as they would be reported by a device tree description.
515    pub flags: ArmSmmuIrqFlags,
516}
517
518#[repr(C)]
519#[derive(Clone, Copy, Debug, Eq, PartialEq)]
520pub struct DcfgArmSmmuDriver {
521    /// Base physical address of the SMMU address space.  This is also the start of
522    /// Global Register Space 0 in the SMMU.  The effective size of these registers
523    /// will be determined at runtime from the ID registers present in this first
524    /// page, specifically the number of context banks in IDR1.NUMCB.
525    ///
526    /// See:
527    ///
528    /// ARM System Memory Management Unit Architecture Specification
529    /// SMMU architecture version 2.0
530    /// ARM IHI 0062D.c
531    ///
532    /// for more details.
533    pub mmio_phys: u64,
534
535    /// The number of context banks that a driver should limit itself to using,
536    /// or 0 if all discovered context banks are available for use.
537    pub num_context_banks_override: u32,
538
539    /// The number of stream match registers that a driver should limit itself
540    /// to using, or 0 if all discovered SMRs are available for use.
541    pub num_smr_override: u32,
542
543    /// An array of context bank interrupt definitions discovered during device
544    /// enumeration.  |irq_cnt| reports the total number of valid members while
545    /// |irqs|, while |global_irq_cnt| reports the total number of global
546    /// interrupts in |irqs|, with the rest of the interrupts being context bank
547    /// interrupts.  So:
548    ///
549    /// + IRQs [0, global_irq_cnt) are global interrupts
550    /// + IRQs [global_irq_cnt, irq_cnt) are context bank interrupts
551    ///   corresponding to context banks [0, irq_cnt - global_irq_cnt)
552    pub irq_cnt: u32,
553    pub global_irq_cnt: u32,
554    pub irqs: [DcfgArmSmmuIrq; 128],
555
556    /// An array of stream IDs (defined using SMR value/mask encoding) which are
557    /// being "handed off" from the bootloader to the HLOS.  Downstream drivers
558    /// should take care to preserve the existing configuration for these stream
559    /// ids.  |handoff_smr_cnt| reports the number of members of |handoff_smrs|
560    /// which are valid.
561    ///
562    /// Note:  Stream ID ranges in SMRs are encoded using two 16 bit fields, a
563    /// value field and a mask field.  These two fields are packed into a single
564    /// 32-bit integer, with the mask packed into the upper 16 bits, and the
565    /// value packed into the lower 16 bits.
566    pub handoff_smr_cnt: u32,
567    pub handoff_smrs: [u32; 16],
568}
fidl_data_zbi/driver_config.rs

fidl_data_zbi/
driver_config.rs
