fidl_data_zbi/
driver_config.rs

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1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use bitflags::bitflags;
11use zerocopy::{FromBytes, IntoBytes};
12
13/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
14#[repr(u32)]
15#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
16pub enum KernelDriver {
17    /// 'PSCI'
18    ArmPsci = 0x49435350,
19
20    /// 'GIC2'
21    ArmGicV2 = 0x32434947,
22
23    /// 'GIC3'
24    ArmGicV3 = 0x33434947,
25
26    /// 'ATIM'
27    ArmGenericTimer = 0x4d495441,
28
29    /// 'PL0U'
30    Pl011Uart = 0x55304c50,
31
32    /// 'AMLU'
33    AmlogicUart = 0x554c4d41,
34
35    /// 'AMLH'
36    AmlogicHdcp = 0x484c4d41,
37
38    /// 'DW8U'
39    Dw8250Uart = 0x44573855,
40
41    /// 'RMLH' (typoed, originally intended to by 'AMLR')
42    AmlogicRngV1 = 0x484c4d52,
43
44    /// 'AMLR'
45    AmlogicRngV2 = 0x524c4d41,
46
47    /// 'WD32'
48    Generic32Watchdog = 0x32334457,
49
50    /// 'GENI'
51    GeniUart = 0x494E4547,
52
53    /// '8250'
54    I8250PioUart = 0x30353238,
55
56    /// '825M'
57    I8250Mmio32Uart = 0x4d353238,
58
59    /// '825B'
60    I8250Mmio8Uart = 0x42353238,
61
62    /// 'MMTP'
63    MotmotPower = 0x4d4d5450,
64
65    /// '370P'
66    As370Power = 0x50303733,
67
68    /// 'MNFP'
69    MoonflowerPower = 0x4d4e4650,
70
71    /// 'IMXU'
72    ImxUart = 0x55584d49,
73
74    /// 'PLIC'
75    RiscvPlic = 0x43494C50,
76
77    /// 'RTIM'
78    RiscvGenericTimer = 0x4D495452,
79
80    /// 'PXAU'
81    PxaUart = 0x50584155,
82
83    /// 'EXYU'
84    ExynosUsiUart = 0x45585955,
85}
86
87/// Kernel driver struct that can be used for simple drivers.
88/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
89/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
90#[repr(C)]
91#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
92pub struct DcfgSimple {
93    pub mmio_phys: u64,
94    pub irq: u32,
95    pub flags: u32,
96}
97
98#[repr(C)]
99#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
100pub struct KernelDriverIrqFlags(u32);
101
102bitflags! {
103    impl KernelDriverIrqFlags : u32 {
104
105        /// When no flag is set, implies no information was obtained, and the
106        /// kernel will apply default configuration as it sees fit.
107        const EDGE_TRIGGERED = 1 << 0;
108        const LEVEL_TRIGGERED = 1 << 1;
109
110        /// Interpretation depends on whether is edge or level triggered.
111        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
112        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
113        const POLARITY_LOW = 1 << 2;
114
115        /// Interpretation depends on whether is edge or level triggered.
116        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
117        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
118        const POLARITY_HIGH = 1 << 3;
119  }
120}
121
122/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
123#[repr(C)]
124#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
125pub struct DcfgSimplePio {
126    pub base: u16,
127    pub reserved: u16,
128    pub irq: u32,
129}
130
131/// for ZBI_KERNEL_DRIVER_ARM_PSCI
132#[repr(C)]
133#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
134pub struct DcfgArmPsciDriver {
135    pub use_hvc: u8,
136    pub reserved: [u8; 7],
137    pub shutdown_args: [u64; 3],
138    pub reboot_args: [u64; 3],
139    pub reboot_bootloader_args: [u64; 3],
140    pub reboot_recovery_args: [u64; 3],
141}
142
143/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
144#[repr(C)]
145#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
146pub struct DcfgArmGicV2Driver {
147    pub mmio_phys: u64,
148    pub msi_frame_phys: u64,
149    pub gicd_offset: u64,
150    pub gicc_offset: u64,
151    pub gich_offset: u64,
152    pub gicv_offset: u64,
153    pub ipi_base: u32,
154    pub optional: u8,
155    pub use_msi: u8,
156    pub reserved: u16,
157}
158
159/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
160#[repr(C)]
161#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
162pub struct DcfgArmGicV3Driver {
163    pub mmio_phys: u64,
164    pub gicd_offset: u64,
165    pub gicr_offset: u64,
166    pub gicr_stride: u64,
167    pub reserved0: u64,
168    pub ipi_base: u32,
169    pub optional: u8,
170    pub reserved1: [u8; 3],
171}
172
173/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
174#[repr(C)]
175#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
176pub struct DcfgArmGenericTimerDriver {
177    pub irq_phys: u32,
178    pub irq_virt: u32,
179    pub irq_sphys: u32,
180    pub freq_override: u32,
181}
182
183/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
184#[repr(C)]
185#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
186pub struct DcfgAmlogicHdcpDriver {
187    pub preset_phys: u64,
188    pub hiu_phys: u64,
189    pub hdmitx_phys: u64,
190}
191
192/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V1
193/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V2
194#[repr(C)]
195#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
196pub struct DcfgAmlogicRngDriver {
197    pub rng_data_phys: u64,
198    pub rng_status_phys: u64,
199    pub rng_refresh_interval_usec: u64,
200}
201
202/// Defines a register write action for a generic kernel watchdog driver.  An
203/// action consists of the following steps.
204///
205/// 1) Read from the register located a physical address |addr|
206/// 2) Clear all of the bits in the value which was read using the |clr_mask|
207/// 3) Set all of the bits in the value using the |set_mask|
208/// 4) Write this value back to the address located at addr
209#[repr(C)]
210#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
211pub struct DcfgGeneric32WatchdogAction {
212    pub addr: u64,
213    pub clr_mask: u32,
214    pub set_mask: u32,
215}
216
217#[repr(C)]
218#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
219pub struct KernelDriverGeneric32WatchdogFlags(u32);
220
221bitflags! {
222    impl KernelDriverGeneric32WatchdogFlags : u32 {
223        const ENABLED = 1 << 0;
224  }
225}
226
227/// 1ms
228pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;
229
230/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
231/// kernel driver which may be passed by a bootloader.  Field definitions are as
232/// follows.
233#[repr(C)]
234#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
235pub struct DcfgGeneric32Watchdog {
236    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
237    pub pet_action: DcfgGeneric32WatchdogAction,
238
239    /// The address and masks needed to enable a hardware watchdog timer.  If enable
240    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
241    pub enable_action: DcfgGeneric32WatchdogAction,
242
243    /// The address and masks needed to disable a hardware watchdog timer.  If
244    /// disable is an unsupported operation, the addr of the |disable_action| shall
245    /// be zero.
246    pub disable_action: DcfgGeneric32WatchdogAction,
247
248    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
249    /// watchdog timer driver must pet the watch dog at least this often.  The value
250    /// must be at least 1 mSec, typically much larger (on the order of a second or
251    /// two).
252    pub watchdog_period_nsec: i64,
253
254    /// Storage for additional flags.  Currently, only one flag is defined,
255    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
256    /// was left enabled by the bootloader at startup.
257    pub flags: KernelDriverGeneric32WatchdogFlags,
258    pub reserved: u32,
259}
260
261/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
262#[repr(C)]
263#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
264pub struct DcfgRiscvPlicDriver {
265    pub mmio_phys: u64,
266    pub num_irqs: u32,
267    pub reserved: u32,
268}
269
270/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
271#[repr(C)]
272#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
273pub struct DcfgRiscvGenericTimerDriver {
274    pub freq_hz: u32,
275    pub reserved: u32,
276}
fidl_data_zbi/driver_config.rs

fidl_data_zbi/
driver_config.rs
