fidl_data_zbi/

driver_config.rs

// Copyright 2022 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

// DO NOT EDIT.
// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.

#![allow(unused_imports)]

use bitflags::bitflags;
use zerocopy::{FromBytes, IntoBytes};

/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
#[repr(u32)]
#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
pub enum KernelDriver {
    /// 'PSCI'
    ArmPsci = 0x49435350,

    /// 'GIC2'
    ArmGicV2 = 0x32434947,

    /// 'GIC3'
    ArmGicV3 = 0x33434947,

    /// 'ATIM'
    ArmGenericTimer = 0x4d495441,

    /// 'PL0U'
    Pl011Uart = 0x55304c50,

    /// 'AMLU'
    AmlogicUart = 0x554c4d41,

    /// 'AMLH'
    AmlogicHdcp = 0x484c4d41,

    /// 'DW8U'
    Dw8250Uart = 0x44573855,

    /// 'RMLH' (typoed, originally intended to by 'AMLR')
    AmlogicRngV1 = 0x484c4d52,

    /// 'AMLR'
    AmlogicRngV2 = 0x524c4d41,

    /// 'WD32'
    Generic32Watchdog = 0x32334457,

    /// 'GENI'
    GeniUart = 0x494E4547,

    /// '8250'
    I8250PioUart = 0x30353238,

    /// '825M'
    I8250Mmio32Uart = 0x4d353238,

    /// '825B'
    I8250Mmio8Uart = 0x42353238,

    /// 'MMTP'
    MotmotPower = 0x4d4d5450,

    /// '370P'
    As370Power = 0x50303733,

    /// 'IMXU'
    ImxUart = 0x55584d49,

    /// 'PLIC'
    RiscvPlic = 0x43494C50,

    /// 'RTIM'
    RiscvGenericTimer = 0x4D495452,

    /// 'PXAU'
    PxaUart = 0x50584155,

    /// 'EXYU'
    ExynosUsiUart = 0x45585955,
}

/// Kernel driver struct that can be used for simple drivers.
/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgSimple {
    pub mmio_phys: u64,
    pub irq: u32,
    pub flags: u32,
}

#[repr(C)]
#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub struct KernelDriverIrqFlags(u32);

bitflags! {
    impl KernelDriverIrqFlags : u32 {

        /// When no flag is set, implies no information was obtained, and the
        /// kernel will apply default configuration as it sees fit.
        const EDGE_TRIGGERED = 1 << 0;
        const LEVEL_TRIGGERED = 1 << 1;

        /// Interpretation depends on whether is edge or level triggered.
        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
        const POLARITY_LOW = 1 << 2;

        /// Interpretation depends on whether is edge or level triggered.
        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
        const POLARITY_HIGH = 1 << 3;
  }
}

/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgSimplePio {
    pub base: u16,
    pub reserved: u16,
    pub irq: u32,
}

/// for ZBI_KERNEL_DRIVER_ARM_PSCI
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgArmPsciDriver {
    pub use_hvc: u8,
    pub reserved: [u8; 7],
    pub shutdown_args: [u64; 3],
    pub reboot_args: [u64; 3],
    pub reboot_bootloader_args: [u64; 3],
    pub reboot_recovery_args: [u64; 3],
}

/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgArmGicV2Driver {
    pub mmio_phys: u64,
    pub msi_frame_phys: u64,
    pub gicd_offset: u64,
    pub gicc_offset: u64,
    pub gich_offset: u64,
    pub gicv_offset: u64,
    pub ipi_base: u32,
    pub optional: u8,
    pub use_msi: u8,
    pub reserved: u16,
}

/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgArmGicV3Driver {
    pub mmio_phys: u64,
    pub gicd_offset: u64,
    pub gicr_offset: u64,
    pub gicr_stride: u64,
    pub reserved0: u64,
    pub ipi_base: u32,
    pub optional: u8,
    pub reserved1: [u8; 3],
}

/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgArmGenericTimerDriver {
    pub irq_phys: u32,
    pub irq_virt: u32,
    pub irq_sphys: u32,
    pub freq_override: u32,
}

/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgAmlogicHdcpDriver {
    pub preset_phys: u64,
    pub hiu_phys: u64,
    pub hdmitx_phys: u64,
}

/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V1
/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V2
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgAmlogicRngDriver {
    pub rng_data_phys: u64,
    pub rng_status_phys: u64,
    pub rng_refresh_interval_usec: u64,
}

/// Defines a register write action for a generic kernel watchdog driver.  An
/// action consists of the following steps.
///
/// 1) Read from the register located a physical address |addr|
/// 2) Clear all of the bits in the value which was read using the |clr_mask|
/// 3) Set all of the bits in the value using the |set_mask|
/// 4) Write this value back to the address located at addr
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgGeneric32WatchdogAction {
    pub addr: u64,
    pub clr_mask: u32,
    pub set_mask: u32,
}

#[repr(C)]
#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub struct KernelDriverGeneric32WatchdogFlags(u32);

bitflags! {
    impl KernelDriverGeneric32WatchdogFlags : u32 {
        const ENABLED = 1 << 0;
  }
}

/// 1ms
pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;

/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
/// kernel driver which may be passed by a bootloader.  Field definitions are as
/// follows.
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgGeneric32Watchdog {
    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
    pub pet_action: DcfgGeneric32WatchdogAction,

    /// The address and masks needed to enable a hardware watchdog timer.  If enable
    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
    pub enable_action: DcfgGeneric32WatchdogAction,

    /// The address and masks needed to disable a hardware watchdog timer.  If
    /// disable is an unsupported operation, the addr of the |disable_action| shall
    /// be zero.
    pub disable_action: DcfgGeneric32WatchdogAction,

    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
    /// watchdog timer driver must pet the watch dog at least this often.  The value
    /// must be at least 1 mSec, typically much larger (on the order of a second or
    /// two).
    pub watchdog_period_nsec: i64,

    /// Storage for additional flags.  Currently, only one flag is defined,
    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
    /// was left enabled by the bootloader at startup.
    pub flags: KernelDriverGeneric32WatchdogFlags,
    pub reserved: u32,
}

/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgRiscvPlicDriver {
    pub mmio_phys: u64,
    pub num_irqs: u32,
    pub reserved: u32,
}

/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
#[repr(C)]
#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
pub struct DcfgRiscvGenericTimerDriver {
    pub freq_hz: u32,
    pub reserved: u32,
}