fidl_data_zbi/
driver_config.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use bitflags::bitflags;
11use zerocopy::{FromBytes, IntoBytes};
12
13/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
14#[repr(u32)]
15#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
16pub enum KernelDriver {
17    /// 'PSCI'
18    ArmPsci = 0x49435350,
19
20    /// 'PSCS'
21    ArmPsciCpuSuspend = 0x53435350,
22
23    /// 'GIC2'
24    ArmGicV2 = 0x32434947,
25
26    /// 'GIC3'
27    ArmGicV3 = 0x33434947,
28
29    /// 'ATIM'
30    ArmGenericTimer = 0x4d495441,
31
32    /// 'ATMM'
33    ArmGenericTimerMmio = 0x4d4d5441,
34
35    /// 'PL0U'
36    Pl011Uart = 0x55304c50,
37
38    /// 'AMLU'
39    AmlogicUart = 0x554c4d41,
40
41    /// 'AMLH'
42    AmlogicHdcp = 0x484c4d41,
43
44    /// 'DW8U'
45    Dw8250Uart = 0x44573855,
46
47    /// 'RMLH' (typoed, originally intended to by 'AMLR')
48    AmlogicRngV1 = 0x484c4d52,
49
50    /// 'AMLR'
51    AmlogicRngV2 = 0x524c4d41,
52
53    /// 'WD32'
54    Generic32Watchdog = 0x32334457,
55
56    /// 'GENI'
57    GeniUart = 0x494E4547,
58
59    /// '8250'
60    I8250PioUart = 0x30353238,
61
62    /// '825M'
63    I8250Mmio32Uart = 0x4d353238,
64
65    /// '825B'
66    I8250Mmio8Uart = 0x42353238,
67
68    /// 'MMTP'
69    MotmotPower = 0x4d4d5450,
70
71    /// '370P'
72    As370Power = 0x50303733,
73
74    /// 'MNFP'
75    MoonflowerPower = 0x4d4e4650,
76
77    /// 'IMXU'
78    ImxUart = 0x55584d49,
79
80    /// 'PLIC'
81    RiscvPlic = 0x43494C50,
82
83    /// 'RTIM'
84    RiscvGenericTimer = 0x4D495452,
85
86    /// 'PXAU'
87    PxaUart = 0x50584155,
88
89    /// 'EXYU'
90    ExynosUsiUart = 0x45585955,
91
92    /// `QRNG`
93    QcomRng = 0x474E5251,
94}
95
96/// Kernel driver struct that can be used for simple drivers.
97/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
98/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
99#[repr(C)]
100#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
101pub struct DcfgSimple {
102    pub mmio_phys: u64,
103    pub irq: u32,
104    pub flags: u32,
105}
106
107#[repr(C)]
108#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
109pub struct KernelDriverIrqFlags(u32);
110
111bitflags! {
112    impl KernelDriverIrqFlags : u32 {
113
114        /// When no flag is set, implies no information was obtained, and the
115        /// kernel will apply default configuration as it sees fit.
116        const EDGE_TRIGGERED = 1 << 0;
117        const LEVEL_TRIGGERED = 1 << 1;
118
119        /// Interpretation depends on whether is edge or level triggered.
120        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
121        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
122        const POLARITY_LOW = 1 << 2;
123
124        /// Interpretation depends on whether is edge or level triggered.
125        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
126        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
127        const POLARITY_HIGH = 1 << 3;
128  }
129}
130
131/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
132#[repr(C)]
133#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
134pub struct DcfgSimplePio {
135    pub base: u16,
136    pub reserved: u16,
137    pub irq: u32,
138}
139
140/// for ZBI_KERNEL_DRIVER_ARM_PSCI
141#[repr(C)]
142#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
143pub struct DcfgArmPsciDriver {
144    pub use_hvc: u8,
145    pub reserved: [u8; 7],
146    pub shutdown_args: [u64; 3],
147    pub reboot_args: [u64; 3],
148    pub reboot_bootloader_args: [u64; 3],
149    pub reboot_recovery_args: [u64; 3],
150}
151
152/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
153#[repr(C)]
154#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
155pub struct DcfgArmGicV2Driver {
156    pub mmio_phys: u64,
157    pub msi_frame_phys: u64,
158    pub gicd_offset: u64,
159    pub gicc_offset: u64,
160    pub gich_offset: u64,
161    pub gicv_offset: u64,
162    pub ipi_base: u32,
163    pub optional: u8,
164    pub use_msi: u8,
165    pub reserved: u16,
166}
167
168/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
169#[repr(C)]
170#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
171pub struct DcfgArmGicV3Driver {
172    pub mmio_phys: u64,
173    pub gicd_offset: u64,
174    pub gicr_offset: u64,
175    pub gicr_stride: u64,
176    pub reserved0: u64,
177    pub ipi_base: u32,
178    pub optional: u8,
179    pub reserved1: [u8; 3],
180}
181
182/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
183#[repr(C)]
184#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
185pub struct DcfgArmGenericTimerDriver {
186    pub irq_phys: u32,
187    pub irq_virt: u32,
188    pub irq_sphys: u32,
189    pub freq_override: u32,
190}
191
192#[repr(C)]
193#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
194pub struct DcfgArmGenericTimerMmioFrame {
195    /// Base address for the frame's EL1 view.
196    pub mmio_phys_el1: u64,
197
198    /// Base address for the frame's EL0 view.
199    /// This is optional.
200    pub mmio_phys_el0: u64,
201
202    /// IRQ information for physical timer. This is mandatory.
203    pub irq_phys: u32,
204
205    /// Same scheme as `DcfgSimple::irq`. This is mandatory.
206    pub irq_phys_flags: u32,
207
208    /// IRQ information for virtual timer.
209    /// This is optional.
210    /// When is not present both `irq_virt` and `irq_virt_flags` will be zero.
211    pub irq_virt: u32,
212
213    /// Same scheme as `DcfgSimple::irq`.
214    pub irq_virt_flags: u32,
215}
216
217/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER_MMIO
218#[repr(C)]
219#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
220pub struct DcfgArmGenericTimerMmioDriver {
221    /// Base address of `CNTCTLBase` frame.
222    pub mmio_phys: u64,
223
224    /// The frequency of the main counter for the timer.
225    pub frequency: u32,
226
227    /// Bitmask containing the set of active frames.
228    /// The `i-th` frame is considered active iff the `i`-th bit is set.
229    /// Note: While there may be up to 8 frames, both missing and disabled frames are treated
230    /// as inactive. Disabled frame information will be present, while missing frames will be zeroed.
231    pub active_frames_mask: u8,
232    pub reserved0: [u8; 3],
233
234    /// Information for each individual frame.
235    /// Inactive frames must be zero-filled.
236    pub frames: [DcfgArmGenericTimerMmioFrame; 8],
237}
238
239/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
240#[repr(C)]
241#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
242pub struct DcfgAmlogicHdcpDriver {
243    pub preset_phys: u64,
244    pub hiu_phys: u64,
245    pub hdmitx_phys: u64,
246}
247
248/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V1
249/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V2
250#[repr(C)]
251#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
252pub struct DcfgAmlogicRngDriver {
253    pub rng_data_phys: u64,
254    pub rng_status_phys: u64,
255    pub rng_refresh_interval_usec: u64,
256}
257
258/// Defines a register write action for a generic kernel watchdog driver.  An
259/// action consists of the following steps.
260///
261/// 1) Read from the register located a physical address |addr|
262/// 2) Clear all of the bits in the value which was read using the |clr_mask|
263/// 3) Set all of the bits in the value using the |set_mask|
264/// 4) Write this value back to the address located at addr
265#[repr(C)]
266#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
267pub struct DcfgGeneric32WatchdogAction {
268    pub addr: u64,
269    pub clr_mask: u32,
270    pub set_mask: u32,
271}
272
273#[repr(C)]
274#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
275pub struct KernelDriverGeneric32WatchdogFlags(u32);
276
277bitflags! {
278    impl KernelDriverGeneric32WatchdogFlags : u32 {
279        const ENABLED = 1 << 0;
280  }
281}
282
283/// 1ms
284pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;
285
286/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
287/// kernel driver which may be passed by a bootloader.  Field definitions are as
288/// follows.
289#[repr(C)]
290#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
291pub struct DcfgGeneric32Watchdog {
292    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
293    pub pet_action: DcfgGeneric32WatchdogAction,
294
295    /// The address and masks needed to enable a hardware watchdog timer.  If enable
296    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
297    pub enable_action: DcfgGeneric32WatchdogAction,
298
299    /// The address and masks needed to disable a hardware watchdog timer.  If
300    /// disable is an unsupported operation, the addr of the |disable_action| shall
301    /// be zero.
302    pub disable_action: DcfgGeneric32WatchdogAction,
303
304    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
305    /// watchdog timer driver must pet the watch dog at least this often.  The value
306    /// must be at least 1 mSec, typically much larger (on the order of a second or
307    /// two).
308    pub watchdog_period_nsec: i64,
309
310    /// Storage for additional flags.  Currently, only one flag is defined,
311    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
312    /// was left enabled by the bootloader at startup.
313    pub flags: KernelDriverGeneric32WatchdogFlags,
314    pub reserved: u32,
315}
316
317/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
318#[repr(C)]
319#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
320pub struct DcfgRiscvPlicDriver {
321    /// Physical address of the PLIC MMIO region.
322    pub mmio_phys: u64,
323
324    /// Size in bytes of the PLIC MMIO region.
325    pub size_bytes: u32,
326
327    /// Number of supported IRQs.
328    pub num_irqs: u32,
329}
330
331/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
332#[repr(C)]
333#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
334pub struct DcfgRiscvGenericTimerDriver {
335    pub freq_hz: u32,
336    pub reserved: u32,
337}
338
339#[repr(C)]
340#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
341pub struct ArmPsciCpuSuspendStateFlags(u32);
342
343bitflags! {
344    impl ArmPsciCpuSuspendStateFlags : u32 {
345
346        /// If set, when entering the associated low power state the CPU's architectural timer will be
347        /// turned off, making it an unsuitable source for exiting the low power state.
348        /// A different source must be programmed.
349        const LOCAL_TIMER_STOPS = 1 << 0;
350
351        /// If set, the PSCI CPU Suspend operation will affect the entire power domain, implying all other
352        /// CPUs of the power domain must be in a low power mode. That is, the last CPU in the power
353        /// domain is the one to enter this power state.
354        const TARGETS_POWER_DOMAIN = 1 << 1;
355  }
356}
357
358/// The ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND's payload consists on any number of
359/// `DcfgArmPsciCpuSuspendState` entries.
360///
361/// The length of the item is `sizeof(zbi_dcfg_arm_psci_cou_suspend_state_t)` times the number of
362/// entries. Each entry describes an 'idle state' that can be entered through PSCI CPU Suspend call.
363///
364/// Entries in the table may be in any order, and only a single item of type
365/// ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND should be present in the ZBI.
366#[repr(C)]
367#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
368pub struct DcfgArmPsciCpuSuspendState {
369    /// Unique identifier representing this suspend state.
370    pub id: u32,
371
372    /// PSCI power_state as described in "Section 5.4.2. of Arm Power State Coordination Interface"
373    /// v1.3.
374    pub power_state: u32,
375    pub flags: ArmPsciCpuSuspendStateFlags,
376
377    /// Latency in microseconds to enter the low power state.
378    pub entry_latency_us: u32,
379
380    /// Latency in microseconds to exit the low power state.
381    pub exit_latency_us: u32,
382
383    /// Minimum time in microseconds, including `entry_latency`, to stay in this low power state.
384    /// Spending less time would be inefficient energy-wise.
385    pub min_residency_us: u32,
386}
387
388#[repr(C)]
389#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
390pub struct QcomRngFlags(u32);
391
392bitflags! {
393    impl QcomRngFlags : u32 {
394
395        /// The driver has been handed off, configured and initialized.
396        const ENABLED = 1 << 0;
397  }
398}
399
400#[repr(C)]
401#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
402pub struct DcfgQcomRng {
403    /// Base address of the register banks for the device.
404    pub mmio_phys: u64,
405    pub flags: QcomRngFlags,
406    pub reserved: [u8; 4],
407}
fidl_data_zbi/driver_config.rs

fidl_data_zbi/
driver_config.rs
