bind_fuchsia_pci/
fuchsia_pci_lib.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// WARNING: This file is machine generated by bindc.
6
7#![allow(unused_crate_dependencies)]
8
9
10pub const BIND_PROTOCOL_DEVICE: u32 = 31;
11pub const BIND_PROTOCOL_ROOT: u32 = 32;
12
13pub const BIND_PCI_VID_TEST: u32 = 3839;
14pub const BIND_PCI_VID_AMD: u32 = 4098;
15pub const BIND_PCI_VID_REALTEK: u32 = 4332;
16pub const BIND_PCI_VID_NVIDIA: u32 = 4318;
17pub const BIND_PCI_VID_GOOGLE: u32 = 6880;
18pub const BIND_PCI_VID_VIRTIO: u32 = 6900;
19pub const BIND_PCI_VID_BROADCOM: u32 = 5348;
20pub const BIND_PCI_VID_ATHEROS: u32 = 5772;
21pub const BIND_PCI_VID_INTEL: u32 = 32902;
22
23pub const BIND_PCI_DID_TEST: u32 = 4095;
24pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_NETWORK: u32 = 4161;
25pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_BLOCK: u32 = 4162;
26pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_BALLOON: u32 = 4173;
27pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_CONSOLE: u32 = 4163;
28pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_SCSI: u32 = 4168;
29pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_ENTROPY: u32 = 4164;
30pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_GPU: u32 = 4176;
31pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_INPUT: u32 = 4178;
32pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_SOCKET: u32 = 4179;
33pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_PMEM: u32 = 4187;
34pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_NETWORK: u32 = 4096;
35pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_BLOCK: u32 = 4097;
36pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_BALLOON: u32 = 4098;
37pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_CONSOLE: u32 = 4099;
38pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_SCSI_HOST: u32 = 4100;
39pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_ENTROPY: u32 = 4101;
40pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_9P: u32 = 4105;
41pub const BIND_PCI_DID_RTL8111: u32 = 33128;
42pub const BIND_PCI_DID_INTEL_SPT_SPI0: u32 = 40233;
43pub const BIND_PCI_DID_GOOGLE_GRAPHICS_ADAPTER: u32 = 40962;
44
45pub const BIND_PCI_CLASS_UNCLASSIFIED: u32 = 0;
46pub const BIND_PCI_CLASS_MASS_STORAGE: u32 = 1;
47pub const BIND_PCI_CLASS_NETWORK: u32 = 2;
48pub const BIND_PCI_CLASS_DISPLAY: u32 = 3;
49pub const BIND_PCI_CLASS_MULTIMEDIA: u32 = 4;
50pub const BIND_PCI_CLASS_MEMORY_CONTROLLER: u32 = 5;
51pub const BIND_PCI_CLASS_BRIDGE: u32 = 6;
52pub const BIND_PCI_CLASS_COMMUNICATION_CONTROLLER: u32 = 7;
53pub const BIND_PCI_CLASS_GENERIC_SYSTEM_PERIPHERAL: u32 = 8;
54pub const BIND_PCI_CLASS_INPUT_DEVICE_CONTROLLER: u32 = 9;
55pub const BIND_PCI_CLASS_DOCKING_STATION: u32 = 10;
56pub const BIND_PCI_CLASS_PROCESSOR: u32 = 11;
57pub const BIND_PCI_CLASS_SERIAL_BUS_CONTROLLER: u32 = 12;
58pub const BIND_PCI_CLASS_WIRELESS_CONTROLLER: u32 = 13;
59pub const BIND_PCI_CLASS_INTELLIGENT_CONTROLLER: u32 = 14;
60pub const BIND_PCI_CLASS_SATELLITE_COMMUNICATIONS_CONTROLLER: u32 = 15;
61pub const BIND_PCI_CLASS_ENCRYPTION_CONTROLLER: u32 = 16;
62pub const BIND_PCI_CLASS_SIGNAL_PROCESSING_CONTROLLER: u32 = 17;
63pub const BIND_PCI_CLASS_PROCESSING_ACCELERATORS: u32 = 18;
64pub const BIND_PCI_CLASS_NONESSENTIAL_INSTRUMENTATION: u32 = 19;
65pub const BIND_PCI_CLASS_COPROCESSOR: u32 = 64;
66pub const BIND_PCI_CLASS_UNASSIGNED: u32 = 255;
bind_fuchsia_pci/fuchsia_pci_lib.rs

bind_fuchsia_pci/
fuchsia_pci_lib.rs
