bind_fuchsia_pci/
fuchsia_pci_lib.rs

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// Copyright 2022 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

// WARNING: This file is machine generated by bindc.


pub const BIND_PROTOCOL_DEVICE: u32 = 31;
pub const BIND_PROTOCOL_ROOT: u32 = 32;

pub const BIND_PCI_VID_TEST: u32 = 3839;
pub const BIND_PCI_VID_AMD: u32 = 4098;
pub const BIND_PCI_VID_REALTEK: u32 = 4332;
pub const BIND_PCI_VID_NVIDIA: u32 = 4318;
pub const BIND_PCI_VID_GOOGLE: u32 = 6880;
pub const BIND_PCI_VID_VIRTIO: u32 = 6900;
pub const BIND_PCI_VID_BROADCOM: u32 = 5348;
pub const BIND_PCI_VID_ATHEROS: u32 = 5772;
pub const BIND_PCI_VID_INTEL: u32 = 32902;

pub const BIND_PCI_DID_TEST: u32 = 4095;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_NETWORK: u32 = 4161;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_BLOCK: u32 = 4162;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_BALLOON: u32 = 4173;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_CONSOLE: u32 = 4163;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_SCSI: u32 = 4168;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_ENTROPY: u32 = 4164;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_GPU: u32 = 4176;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_INPUT: u32 = 4178;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_SOCKET: u32 = 4179;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_NETWORK: u32 = 4096;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_BLOCK: u32 = 4097;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_BALLOON: u32 = 4098;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_CONSOLE: u32 = 4099;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_SCSI_HOST: u32 = 4100;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_ENTROPY: u32 = 4101;
pub const BIND_PCI_DID_VIRTIO_DEV_TYPE_T_9P: u32 = 4105;
pub const BIND_PCI_DID_RTL8111: u32 = 33128;
pub const BIND_PCI_DID_INTEL_SPT_SPI0: u32 = 40233;
pub const BIND_PCI_DID_GOOGLE_GRAPHICS_ADAPTER: u32 = 40962;

pub const BIND_PCI_CLASS_UNCLASSIFIED: u32 = 0;
pub const BIND_PCI_CLASS_MASS_STORAGE: u32 = 1;
pub const BIND_PCI_CLASS_NETWORK: u32 = 2;
pub const BIND_PCI_CLASS_DISPLAY: u32 = 3;
pub const BIND_PCI_CLASS_MULTIMEDIA: u32 = 4;
pub const BIND_PCI_CLASS_MEMORY_CONTROLLER: u32 = 5;
pub const BIND_PCI_CLASS_BRIDGE: u32 = 6;
pub const BIND_PCI_CLASS_COMMUNICATION_CONTROLLER: u32 = 7;
pub const BIND_PCI_CLASS_GENERIC_SYSTEM_PERIPHERAL: u32 = 8;
pub const BIND_PCI_CLASS_INPUT_DEVICE_CONTROLLER: u32 = 9;
pub const BIND_PCI_CLASS_DOCKING_STATION: u32 = 10;
pub const BIND_PCI_CLASS_PROCESSOR: u32 = 11;
pub const BIND_PCI_CLASS_SERIAL_BUS_CONTROLLER: u32 = 12;
pub const BIND_PCI_CLASS_WIRELESS_CONTROLLER: u32 = 13;
pub const BIND_PCI_CLASS_INTELLIGENT_CONTROLLER: u32 = 14;
pub const BIND_PCI_CLASS_SATELLITE_COMMUNICATIONS_CONTROLLER: u32 = 15;
pub const BIND_PCI_CLASS_ENCRYPTION_CONTROLLER: u32 = 16;
pub const BIND_PCI_CLASS_SIGNAL_PROCESSING_CONTROLLER: u32 = 17;
pub const BIND_PCI_CLASS_PROCESSING_ACCELERATORS: u32 = 18;
pub const BIND_PCI_CLASS_NONESSENTIAL_INSTRUMENTATION: u32 = 19;
pub const BIND_PCI_CLASS_COPROCESSOR: u32 = 64;
pub const BIND_PCI_CLASS_UNASSIGNED: u32 = 255;