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Crate fidl_fuchsia_hardware_pci

Crate fidl_fuchsia_hardware_pci 

Source

Modules§

debug_ordinals
device_ordinals

Macros§

BarResultUnknown
Pattern that matches an unknown BarResult member.
CapabilityIdUnknown
Pattern that matches an unknown CapabilityId member.
ConfigUnknown
Pattern that matches an unknown Config member.
ExtendedCapabilityIdUnknown
Pattern that matches an unknown ExtendedCapabilityId member.
HeaderTypeUnknown
Pattern that matches an unknown HeaderType member.

Structs§

Address
An address of a PCI device.
Bar
Describes and provides access to a given Base Address Register for the device.
BaseAddress
Bdf
Bus/device/function address used by the PCI root protocols.
BoardConfiguration
Capability
Command
DebugControlHandle
DebugEventStream
DebugGetDevicesResponder
DebugGetDevicesResponse
DebugGetHostBridgeInfoResponder
DebugGetHostBridgeInfoResponse
DebugMarker
DebugProxy
DebugReadBarRequest
DebugReadBarResponder
DebugReadBarResponse
DebugRequestStream
A Stream of incoming requests for fuchsia.hardware.pci/Debug.
DebugServiceMarker
DebugServiceProxy
DebugSynchronousProxy
DeviceAckInterruptResponder
DeviceControlHandle
DeviceEventStream
DeviceGetBarRequest
DeviceGetBarResponder
DeviceGetBarResponse
DeviceGetBtiRequest
DeviceGetBtiResponder
DeviceGetBtiResponse
DeviceGetCapabilitiesRequest
DeviceGetCapabilitiesResponder
DeviceGetCapabilitiesResponse
DeviceGetDeviceInfoResponder
DeviceGetDeviceInfoResponse
DeviceGetExtendedCapabilitiesRequest
DeviceGetExtendedCapabilitiesResponder
DeviceGetExtendedCapabilitiesResponse
DeviceGetInterruptModesResponder
DeviceGetInterruptModesResponse
DeviceInfo
Device specific information from a device’s configuration header. PCI Local Bus Specification v3, chapter 6.1.
DeviceMapInterruptRequest
DeviceMapInterruptResponder
DeviceMapInterruptResponse
DeviceMarker
DeviceProxy
DeviceReadConfig8Request
DeviceReadConfig8Responder
DeviceReadConfig8Response
DeviceReadConfig16Request
DeviceReadConfig16Responder
DeviceReadConfig16Response
DeviceReadConfig32Request
DeviceReadConfig32Responder
DeviceReadConfig32Response
DeviceRequestStream
A Stream of incoming requests for fuchsia.hardware.pci/Device.
DeviceResetDeviceResponder
DeviceSetBusMasteringRequest
DeviceSetBusMasteringResponder
DeviceSetInterruptModeRequest
DeviceSetInterruptModeResponder
DeviceSynchronousProxy
DeviceWriteConfig8Request
DeviceWriteConfig8Responder
DeviceWriteConfig16Request
DeviceWriteConfig16Responder
DeviceWriteConfig32Request
DeviceWriteConfig32Responder
ExtendedCapability
HostBridgeInfo
InterruptModes
Returned by |GetInterruptModes|. Contains the number of interrupts supported by a given PCI device interrupt mode. 0 is returned for a mode if unsupported.
IoBar
Padding
PciDevice
ServiceMarker
ServiceProxy
Status
UseIntxWorkaroundType

Enums§

BarResult
CapabilityId
PCI Capability ID. PCI Local Bus Specification v3, appendex H.
Config
PCI Configuration Header registers. PCI Local Bus Specification v3, chapter 6.1.
DebugEvent
DebugRequest
The Debug protocol provides information about devices on a particular bus. It is used for tools like lspci and not for driver operations.
DebugServiceRequest
A request for one of the member protocols of DebugService.
DeviceEvent
DeviceRequest
ExtendedCapabilityId
PCI Extended Capability IDs. PCIe Base Specification rev4, chapter 7.6.
HeaderType
InterruptMode
Used with ||SetInterruptMode| to configure an interrupt mode for the device. Devices configured to use the LEGACY Irq mode must ack their interrupt after servicing by calling |AckInterrupt|.
ServiceRequest
A request for one of the member protocols of Service.

Constants§

BASE_ADDRESS_COUNT
BASE_CONFIG_SIZE
Per the PCI specification.
EXTENDED_CONFIG_SIZE
LEGACY_INTERRUPT_COUNT
Legacy interrupt pins INTA through INTD.
MAX_BAR_COUNT
MAX_CAPABILITIES
MAX_DEVICES
At the time of writing, a Device is 571 bytes.
MAX_EXT_CAPABILITIES
MAX_NAME_LEN
READBAR_MAX_SIZE
STATUS_DEVSEL_MASK

Traits§

DebugProxyInterface
DeviceProxyInterface

Type Aliases§

ConfigOffset
An offset from the beginning of a device’s PCI configuration space. [0, 0x100) is valid.
DebugReadBarResult
DeviceAckInterruptResult
DeviceGetBarResult
DeviceGetBtiResult
DeviceMapInterruptResult
DeviceReadConfig8Result
DeviceReadConfig16Result
DeviceReadConfig32Result
DeviceResetDeviceResult
DeviceSetBusMasteringResult
DeviceSetInterruptModeResult
DeviceWriteConfig8Result
DeviceWriteConfig16Result
DeviceWriteConfig32Result
ExtendedConfigOffset
An offset from the beginning of a device’s PCIe configuration space. [0, 0x800) is valid.