Trait fidl_fuchsia_hardware_pci::BusProxyInterface

source · 
pub trait BusProxyInterface: Send + Sync {
    type GetHostBridgeInfoResponseFut: Future<Output = Result<HostBridgeInfo, Error>> + Send;
    type GetDevicesResponseFut: Future<Output = Result<Vec<PciDevice>, Error>> + Send;
    type ReadBarResponseFut: Future<Output = Result<BusReadBarResult, Error>> + Send;

    // Required methods
    fn get_host_bridge_info(&self) -> Self::GetHostBridgeInfoResponseFut;
    fn get_devices(&self) -> Self::GetDevicesResponseFut;
    fn read_bar(
        &self,
        device: &Address,
        bar_id: u8,
        offset: u64,
        size: u64
    ) -> Self::ReadBarResponseFut;
}

Required Associated Types§

source

type GetHostBridgeInfoResponseFut: Future<Output = Result<HostBridgeInfo, Error>> + Send

source

type GetDevicesResponseFut: Future<Output = Result<Vec<PciDevice>, Error>> + Send

source

type ReadBarResponseFut: Future<Output = Result<BusReadBarResult, Error>> + Send

Required Methods§

source

fn get_host_bridge_info(&self) -> Self::GetHostBridgeInfoResponseFut

source

fn get_devices(&self) -> Self::GetDevicesResponseFut

source

fn read_bar( &self, device: &Address, bar_id: u8, offset: u64, size: u64 ) -> Self::ReadBarResponseFut

Implementors§