Enumerations
enum Platform| Name | Value |
|---|---|
| kSkylake | 0 |
| kKabyLake | 1 |
| kTigerLake | 2 |
| kTestDevice | 3 |
Defined at line 15 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
enum PlaneControlAlphaMode| Name | Value |
|---|---|
| kAlphaIgnored | 0 |
| kInvalid | 1 |
| kAlphaPreMultiplied | 2 |
| kAlphaHardwareMultiply | 3 |
Possible values for the `alpha_mode*` fields in plane control registers.
Defined at line 139 of file ../../src/graphics/display/drivers/intel-display/registers-pipe.h
enum PortLane| Name | Value |
|---|---|
| kAux | 0x3 |
| kAll | 0x6 |
| kMainLinkLane0 | 0x8 |
| kMainLinkLane1 | 0x9 |
| kMainLinkLane2 | 0xa |
| kMainLinkLane3 | 0xb |
Identifies a pair of pins used in voltage differential transmission.
The lane usage is documented in the "Mode Set" > "Sequences for MIPI DSI" >
"DSI Transcoder Enable Sequence" section of the display engine PRMs.
Tiger Lake: IHD-OS-TGL-Vol 12-1.22-Rev2.0 page 127
Ice Lake: IHD-OS-ICLLP-Vol 12-1.22-Rev2.0 page 129
Defined at line 620 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
enum DisplayPortMsaBitsPerComponent| Name | Value |
|---|---|
| k6Bpc | 0 |
| k8Bpc | 1 |
| k10Bpc | 2 |
| k12Bpc | 3 |
| k16Bpc | 4 |
Documented values for the DisplayPort MSA MISC0 field's bits 7:5.
The values come from the VESA DisplayPort Standard Version 2.0, Table 2-96
"MSA MISC1 and MISC0 Fields for Pixel Encoding/Colorimetry Format Indication"
at page 158. The table belongs to Section 2.2.4 "MSA Data Transport".
The encoding here is correct for all modes except for RAW, which uses a
different encoding.
TODO(https://fxbug.dev/42056427): This covers a general DisplayPort concept, so it
belongs in a general-purpose DisplayPort support library.
Defined at line 799 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h
enum DisplayPortMsaColorimetry| Name | Value |
|---|---|
| kRgbUnspecifiedLegacy | 0b0'0'00 |
| kCtaSrgb | 0b0'1'00 |
| kRgbWideGamutFixed | 0b0'0'11 |
| kRgbWideGamutFloating | 0b1'0'00 |
| kYCbCr422Bt601 | 0b0'1'01 |
| kYCbCr422Bt709 | 0b1'1'01 |
| kYCbCr444Bt601 | 0b0'1'10 |
| kYCbCr444Bt709 | 0b1'1'10 |
| kAdobeRgb | 0b1'1'00 |
| kDciP3 | 0b0'1'11 |
| kVcpColorProfile | 0b0'1'11 |
Documented values for the DisplayPort MSA MISC0 field's bits 4:1.
The values come from the VESA DisplayPort Standard Version 2.0, Table 2-96
"MSA MISC1 and MISC0 Fields for Pixel Encoding/Colorimetry Format Indication"
at page 158. The table belongs to Section 2.2.4 "MSA Data Transport".
TODO(https://fxbug.dev/42056427): This covers a general DisplayPort concept, so it
belongs in a general-purpose DisplayPort support library.
Defined at line 815 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h
Records
-
class ActiveHeadPointer -
class AllEngineFault -
class ArbiterControl -
class ArbitrationControl -
class ArbitrationControl2 -
class AsCommand -
class AsFaultAddress -
class AsFaultExtra -
class AsFaultStatus -
class AsLockAddress -
class AsMemoryAttributes -
class AsRegisters -
class AsStatus -
class AsTransConfig -
class AsTranslationTable -
class BandwidthBuddyControl -
class BandwidthBuddyPageMask -
class BaseDsm -
class CacheMode1 -
class CdClockCtl -
class ChipDate -
class ChipId -
class ClockControl -
class CoherencyFeatures -
class CoreReadyState -
class CscCoeff -
class CscCoeffFormat -
class CscMode -
class CscOffset -
class CtcMode -
class CursorBase -
class CursorCtrl -
class CursorPos -
class CursorSurfaceLive -
class CustomerId -
class CycleCount -
class DataBufferControl -
class DataBufferControl2 -
class DdiAuxControl -
class DdiAuxData -
class DdiAuxMutex -
class DdiBufferControl -
class DdiClockConfig -
class DdiPhyBalanceControl -
class DdiPhyConfigEntry1 -
class DdiPhyConfigEntry2 -
class DdiRegs -
class DedicatedPathArbiterCredits -
class DekelCommonConfigMicroControllerDword27 -
class DekelDisplayPortMode -
class DekelOpaqueRegister -
class DekelPllBias -
class DekelPllClktop2HighSpeedClockControl -
class DekelPllDivisor0 -
class DekelRegisterAddr -
class DekelRegisterBase -
class DekelTransmitterDisplayPortControl0 -
class DekelTransmitterDisplayPortControl1 -
class DekelTransmitterDisplayPortControl2 -
class DekelTransmitterPmdLaneSus -
class DisplayFuses -
class DisplayInterruptControl -
class DisplayPllControl1 -
class DisplayPllDcoDividersKabyLake -
class DisplayPllDcoDividersTigerLake -
class DisplayPllDcoFrequencyKabyLake -
class DisplayPllDcoFrequencyTigerLake -
class DisplayPllDdiMapKabyLake -
class DisplayPllDivider -
class DisplayPllSpreadSpectrumClocking -
class DisplayPllStatus -
class DisplayResetOptions -
class DisplayStraps -
class DmaAddress -
class DmaDebugState -
class DmaStatus -
class DpTransportControl -
class DynamicFlexIoDisplayPortControllerSafeStateSettings -
class DynamicFlexIoDisplayPortMainLinkLaneEnabled -
class DynamicFlexIoDisplayPortPhyModeStatus -
class DynamicFlexIoDisplayPortPinAssignment -
class DynamicFlexIoScratchPad -
class EcoId -
class ExeclistControl -
class ExeclistStatusGen12 -
class ExeclistStatusGen9 -
class ExeclistSubmitPort -
class ExeclistSubmitQueue -
class FaultTlbReadData -
class Features -
class FetchEngineCommandAddress -
class FetchEngineCommandControl -
class ForceWakeRequest -
class ForceWakeStatus -
class Fuse2ControlDwordMirror -
class FuseStatus -
class GMBusClockPortSelect -
class GMBusCommand -
class GMBusControllerInterruptMask -
class GMBusControllerStatus -
class GMBusData -
class GMBusTwoByteIndex -
class GmchGfxControl -
class GmchGraphicsControl -
class GpioPinPairControl -
class GpuCommand -
class GpuFaultAddress -
class GpuFaultStatus -
class GpuId -
class GpuIrqFlags -
class GpuStatus -
class GraphicsDeviceResetControl -
class GraphicsMode -
class GraphicsPrimaryInterrupt -
class GtInterruptEnable0 -
class GtInterruptEnable0Gen12 -
class GtInterruptEnable1 -
class GtInterruptEnable1Gen12 -
class GtInterruptIdentity0 -
class GtInterruptIdentity1 -
class GtInterruptIdentityGen12 -
class GtInterruptMask0 -
class GtInterruptMask0Gen12 -
class GtInterruptMask1 -
class GtInterruptMask2Gen12 -
class GtInterruptSelector0Gen12 -
class GtInterruptSelector1Gen12 -
class GtInterruptStatus0Gen12 -
class GtInterruptStatus1Gen12 -
class HardwareStatusMask -
class HardwareStatusPageAddress -
class HipIndexReg0 -
class HipIndexReg1 -
class HpdInterruptBase -
class IclCdClkPllEnable -
class IclSouthHotplugCtrl -
class IdleState -
class InterruptRegisterBase -
class IrqAck -
class IrqEnable -
class JobIrqFlags -
class JobJsState -
class JobSlotAffinity -
class JobSlotCommand -
class JobSlotConfig -
class JobSlotFlushId -
class JobSlotHead -
class JobSlotRegisters -
class JobSlotStatus -
class JobSlotTail -
class JobSlotXAffinity -
class L2Features -
class LncfMemoryObjectControlState -
class MasterInterruptControl -
class MbusArbiterBoxControl -
class MbusDisplayBufferBoxControl -
class MbusPipeDataBoxControl -
class MbusUtilityBoxControl -
class MemoryAddressDecoderDimmParametersAlderLake -
class MemoryAddressDecoderDimmParametersCometLake -
class MemoryAddressDecoderDimmParametersSkylake -
class MemoryAddressDecoderInterChannelConfigIceLake -
class MemoryAddressDecoderInterChannelConfigSkylake -
class MemoryChannelTimingsAlderLake -
class MemoryChannelTimingsIceLake -
class MemoryChannelTimingsSkylake -
class MemoryChannelTimingsTigerLake -
class MemoryControllerBiosDataIceLake -
class MemoryControllerBiosDataSkylake -
class MemoryFeatures -
class MemoryObjectControlState -
class MinorFeatures -
class MirrorDssEnable -
class MirrorEuDisable -
class MirrorEuDisableGen12 -
class MmioInfo -
class MmuConfig -
class MmuFeatures -
class MmuIrqFlags -
class MmuNonSecuritySafeAddressLow -
class MmuPageTableArrayConfig -
class MmuSafeAddressConfig -
class MmuSecureControl -
class MmuSecureExceptionAddress -
class MmuSecureStatus -
class MmuSecuritySafeAddressLow -
class PageTableArrayAddressHigh -
class PageTableArrayAddressLow -
class PageTableArrayControl -
class PatIndex -
class PatIndexGen12 -
class PchBacklightControl -
class PchBacklightDuty -
class PchBacklightFreq -
class PchBacklightFreqDuty -
class PchChicken1 -
class PchDisplayFuses -
class PchPanelPowerClockDelay -
class PchPanelPowerControl -
class PchPanelPowerOffDelays -
class PchPanelPowerOnDelays -
class PchPanelPowerStatus -
class PchRawClock -
class PerformanceCounterBase -
class PerformanceCounterConfig -
class PerformanceCounterJmEnable -
class PerformanceCounterMmuL2Enable -
class PerformanceCounterShaderEnable -
class PerformanceCounterTilerEnable -
class PhyMisc -
class PipeArbiterControl -
class PipeBottomColor -
class PipeInterrupt -
class PipeRegs -
class PipeScalerAdaptiveFilterThresholds -
class PipeScalerCoefficientData -
class PipeScalerCoefficientFormat -
class PipeScalerCoefficientIndex -
class PipeScalerCoefficients -
class PipeScalerControlSkylake -
class PipeScalerControlTigerLake -
class PipeScalerHorizontalInitialPhase -
class PipeScalerPowerGateControl -
class PipeScalerRegs -
class PipeScalerScalingFactor -
class PipeScalerVerticalInitialPhase -
class PipeScalerWindowPosition -
class PipeScalerWindowSize -
class PipeSourceSize -
class PlaneBufferConfig -
class PlaneColorControl -
class PlaneControl -
class PlaneKeyMask -
class PlaneKeyMax -
class PlaneOffset -
class PlanePosition -
class PlaneSurface -
class PlaneSurfaceLive -
class PlaneSurfaceSize -
class PlaneSurfaceStride -
class PlaneWm -
class PllEnable -
class PortCommonLane0 -
class PortCommonLane16 -
class PortCommonLane5 -
class PortCommonLaneMainLinkPower -
class PortCommonLaneMiscPower -
class PortCommonLanePowerStatus -
class PortCompensation0 -
class PortCompensation1 -
class PortCompensationLowVoltageReferences -
class PortCompensationNominalVoltageReferences -
class PortCompensationSource -
class PortCompensationStatus -
class PortPhysicalCoding1 -
class PortPhysicalCoding9 -
class PortTransmitter1 -
class PortTransmitterDutyCycleCorrection -
class PortTransmitterEqualization -
class PortTransmitterLowDropoutRegulator -
class PortTransmitterMipiEqualization -
class PortTransmitterNScalar -
class PortTransmitterVoltage -
class PortTransmitterVoltageSwing -
class PowerGateEnable -
class PowerMailboxData0 -
class PowerMailboxData1 -
class PowerMailboxInterface -
class PowerModule -
class PowerWellControl -
class PowerWellControl2 -
class PowerWellControlAux -
class PowerWellControlDdi2 -
class ProductId -
class PulseEater -
class Register -
class RegisterOffset7300 -
class RegistersDevice -
class RegistersDeviceTest -
class RegistersDeviceTestConfig -
class RegistersDeviceTestEnvironment -
class RegistersDeviceTest_OverlappingBitsInTailFailure_Test -
class RegistersDeviceTest_OverlappingBitsTestFailure_Test -
class RegistersDeviceTest_Read32Test_Test -
class RegistersDeviceTest_Read64Test_Test -
class RegistersDeviceTest_Write32Test_Test -
class RegistersDeviceTest_Write64Test_Test -
class RenderEngineTlbControl -
class RenderPerformanceConfig -
class RenderPerformanceNormalFrequencyRequest -
class RenderPerformanceStateCapability -
class RenderPerformanceStatus -
class ResetControl -
class Revision -
class RingbufferHead -
class SdeInterruptBase -
class SecureAhbControl -
class SecureCommandControl -
class ShaderConfig -
class SouthHotplugCtrl -
class Specs1 -
class Specs2 -
class Specs3 -
class Specs4 -
class TbtHotplugCtrl -
class TcHotplugCtrl -
class TestRegistersDevice -
class ThreadFeatures -
class TilerFeatures -
class Timestamp -
class TimestampRegisterPair -
class TransHVSync -
class TransHVTotal -
class TransVSyncShift -
class TranscoderChicken -
class TranscoderClockSelect -
class TranscoderConfig -
class TranscoderDataM -
class TranscoderDataN -
class TranscoderDdiControl -
class TranscoderLinkM -
class TranscoderLinkN -
class TranscoderMainStreamAttributeMisc -
class TranscoderRegs -
class TranscoderVariableRateRefreshControl -
class TypeCDdiClockSelect -
class VgaCtl -
class VideoEngineTlbControl -
class pipe_arming_regs
Functions
-
void PrintRegisters (std::vector<std::string> * dump_out, magma::RegisterIo * io)Defined at line 15 of file ../../src/graphics/drivers/msd-vsi-vip/src/registers.cc
-
template <typename T>size_t GetSize ()Defined at line 37 of file ../../src/devices/registers/drivers/registers/registers.h
-
template <typename T>void WriteHipIndex (T * reg_iointel_display::DdiId ddi_iduint32_t hip_index)Defined at line 736 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h