class DisplayInterruptControl
Defined at line 218 of file ../../src/graphics/display/drivers/intel-display/registers.h
DISPLAY_INT_CTL (Display Interrupt Control)
Controls whether display interrupts propagate to the PCI device interrupt,
and summarizes the pending display interrupts.
This register is referred to as MASTER_INT_CTL (Master Interrupt Control) in
the documentation for Kaby Lake and Skylake.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 1 pages 1054-1055
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 2 pages 9-11
Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 2 pages 10-12
Public Members
field_interrupts_enabled_230 field_pcu_pending_kaby_lake_237 field_audio_codec_pending_240 field_pch_engine_pending_245 field_misc_display_pending_248 field_display_hot_plug_pending_tiger_lake_258 field_port_pending_261 field_pipe_d_pending_tiger_lake_267 field_pipe_c_pending_270 field_pipe_b_pending_273 field_pipe_a_pending_276 field_video_encoding_box_pending_kaby_lake_283 field_gpu_power_pending_kaby_lake_290 field_video_command_streamer_2_pending_kaby_lake_297 field_video_command_streamer_1_pending_kaby_lake_304 field_blitter_pending_kaby_lake_311 field_render_pending_kaby_lake_318Public Methods
template <, >typename SelfType::ValueType interrupts_enabled ()If true, display engine interrupts propagate to the next level.
On Tiger Lake and DG1, display engine interrupts propagate to the graphics
interrupt dispatcher, which is controlled by the GraphicsPrimaryInterrupt
register.
On Kaby Lake and Skylake, display engine interrupts propagate directly to
the PCI device interrupt.
The driver sets this bit when it is ready to process display interrupts.
Defined at line 230 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_interrupts_enabled (typename SelfType::ValueType val)If true, display engine interrupts propagate to the next level.
On Tiger Lake and DG1, display engine interrupts propagate to the graphics
interrupt dispatcher, which is controlled by the GraphicsPrimaryInterrupt
register.
On Kaby Lake and Skylake, display engine interrupts propagate directly to
the PCI device interrupt.
The driver sets this bit when it is ready to process display interrupts.
Defined at line 230 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType pcu_pending_kaby_lake ()True if there are pending interrupts from the PCU (Power Control Unit).
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 237 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_pcu_pending_kaby_lake (typename SelfType::ValueType val)True if there are pending interrupts from the PCU (Power Control Unit).
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 237 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType audio_codec_pending ()True if there are pending interrupts from the audio codec.
Defined at line 240 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_audio_codec_pending (typename SelfType::ValueType val)True if there are pending interrupts from the audio codec.
Defined at line 240 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType pch_engine_pending ()True if there are pending interrupts from the PCH display engine.
If this bit is set, the {{PCH interrupts register}} must be checked.
Defined at line 245 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_pch_engine_pending (typename SelfType::ValueType val)True if there are pending interrupts from the PCH display engine.
If this bit is set, the {{PCH interrupts register}} must be checked.
Defined at line 245 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType misc_display_pending ()True if there are pending miscellaneous display engine interrupts.
Defined at line 248 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_misc_display_pending (typename SelfType::ValueType val)True if there are pending miscellaneous display engine interrupts.
Defined at line 248 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType display_hot_plug_pending_tiger_lake ()True if there are pending hotplug interrupts from the main display engine.
This field only reflects hotplug events from the main / north display
engine. Hotplug interrupts from the PCH / south display engine are recorded
in the `pch_engine_pending` bit.
This bit is not documented on Kaby Lake and Skylake, where the display
engine does not handle hot plug for any port.
Defined at line 258 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_display_hot_plug_pending_tiger_lake (typename SelfType::ValueType val)True if there are pending hotplug interrupts from the main display engine.
This field only reflects hotplug events from the main / north display
engine. Hotplug interrupts from the PCH / south display engine are recorded
in the `pch_engine_pending` bit.
This bit is not documented on Kaby Lake and Skylake, where the display
engine does not handle hot plug for any port.
Defined at line 258 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType port_pending ()True if there are pending port interrupts.
Defined at line 261 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_port_pending (typename SelfType::ValueType val)True if there are pending port interrupts.
Defined at line 261 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType pipe_d_pending_tiger_lake ()True if there are pending Pipe D interrupts.
This field is not documented on Kaby Lake and Skylake. The underlying bit
is reserved but not documented as MBZ (Must Be Zero).
Defined at line 267 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_pipe_d_pending_tiger_lake (typename SelfType::ValueType val)True if there are pending Pipe D interrupts.
This field is not documented on Kaby Lake and Skylake. The underlying bit
is reserved but not documented as MBZ (Must Be Zero).
Defined at line 267 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType pipe_c_pending ()True if there are pending Pipe C interrupts.
Defined at line 270 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_pipe_c_pending (typename SelfType::ValueType val)True if there are pending Pipe C interrupts.
Defined at line 270 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType pipe_b_pending ()True if there are pending Pipe B interrupts.
Defined at line 273 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_pipe_b_pending (typename SelfType::ValueType val)True if there are pending Pipe B interrupts.
Defined at line 273 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType pipe_a_pending ()True if there are pending Pipe A interrupts.
Defined at line 276 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_pipe_a_pending (typename SelfType::ValueType val)True if there are pending Pipe A interrupts.
Defined at line 276 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_video_encoding_box_pending_kaby_lake (typename SelfType::ValueType val)True if there are pending VEBox (video encoding box) interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 283 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType video_encoding_box_pending_kaby_lake ()True if there are pending VEBox (video encoding box) interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 283 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType gpu_power_pending_kaby_lake ()True if there are pending GTPM (GPU power management) interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 290 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_gpu_power_pending_kaby_lake (typename SelfType::ValueType val)True if there are pending GTPM (GPU power management) interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 290 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_video_command_streamer_2_pending_kaby_lake (typename SelfType::ValueType val)True if there are pending VCS (Video Command Streamer) 2 interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 297 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType video_command_streamer_2_pending_kaby_lake ()True if there are pending VCS (Video Command Streamer) 2 interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 297 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_video_command_streamer_1_pending_kaby_lake (typename SelfType::ValueType val)True if there are pending VCS (Video Command Streamer) 1 interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 304 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType video_command_streamer_1_pending_kaby_lake ()True if there are pending VCS (Video Command Streamer) 1 interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 304 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType blitter_pending_kaby_lake ()True if there are pending blitter interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 311 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_blitter_pending_kaby_lake (typename SelfType::ValueType val)True if there are pending blitter interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 311 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType render_pending_kaby_lake ()True if there are pending render interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 318 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_render_pending_kaby_lake (typename SelfType::ValueType val)True if there are pending render interrupts.
This is not documented on Tiger Lake. However, it has good read semantics.
The underlying bit is reserved and documented as MBZ (must be zero), so
reading it will always report that no interrupts are pending.
Defined at line 318 of file ../../src/graphics/display/drivers/intel-display/registers.h
hwreg::RegisterAddr<DisplayInterruptControl> Get ()Defined at line 320 of file ../../src/graphics/display/drivers/intel-display/registers.h