class MemoryAddressDecoderInterChannelConfigSkylake
Defined at line 431 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
MAD_INTER_CHANNEL_0_0_0_MCHBAR (Address decoder inter channel configuration).
Comet Lake: 615212-003 Section 8.33 pages 191-192
Coffee Lake: 337345-003 Section 7.37 page 193
Whiskey Lake: 338024-001 Section 7.10 page 153
Amber Lake: 334662-005 Section 6.31 page 154
Kaby Lake S: 335196-002 Section 7.31 page 186
Kaby Lake H: 335191-003 Section 7.37 page 195
Skylake U: 332991-003 Section 7.31 page 187
Skylake S: 332688-003 Section 7.31 page 169
Skylake H: 332987-003 Section 7.31 page 187
Public Members
field_RsvdZ_442 field_uses_ddr4e_memory_451 field_RsvdZ_453 field_channel_s_size_1gb_464 field_RsvdZ_466 field_channel_l_is_physical_channel1_469 field_enhanced_channel_mode_479 field_ddr_type_select_490Public Methods
template <, >SelfType & set_uses_ddr4e_memory (typename SelfType::ValueType val)True if the attached memory is DDR4-E.
This bit should be zero if `ddr_type_select` does not indicate DDR4.
This bit is only defined on Comet Lake, and is reserved MBZ (must be zero)
on all other platforms. This gives us the right read semantics, as the
feature appears disabled on these platforms.
Defined at line 451 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType uses_ddr4e_memory ()True if the attached memory is DDR4-E.
This bit should be zero if `ddr_type_select` does not indicate DDR4.
This bit is only defined on Comet Lake, and is reserved MBZ (must be zero)
on all other platforms. This gives us the right read semantics, as the
feature appears disabled on these platforms.
Defined at line 451 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType channel_s_size_1gb ()The size of Channel S in 1GB units.
Valid values are 0-64.
This field value is does not match the Comet Lake datasheet. Comet Lake
memory controllers use the field layout in the
`MemoryAddressDecoderInterChannelConfigIceLake` class. `channel_s_size`
uses bits 19:12 and expresses the channel size in multiples of 512 MB. See
`ddr_type_select` for why we use this class for Comet Lake.
Defined at line 464 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_channel_s_size_1gb (typename SelfType::ValueType val)The size of Channel S in 1GB units.
Valid values are 0-64.
This field value is does not match the Comet Lake datasheet. Comet Lake
memory controllers use the field layout in the
`MemoryAddressDecoderInterChannelConfigIceLake` class. `channel_s_size`
uses bits 19:12 and expresses the channel size in multiples of 512 MB. See
`ddr_type_select` for why we use this class for Comet Lake.
Defined at line 464 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType channel_l_is_physical_channel1 ()If false, Channel L is the physical channel 0.
Defined at line 469 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_channel_l_is_physical_channel1 (typename SelfType::ValueType val)If false, Channel L is the physical channel 0.
Defined at line 469 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType enhanced_channel_mode ()If true, the channel operates as two 32-bit channels.
This bit must be true in LPDDR4 configurations, and can be set to
true for LPDDR3. In all other configurations, this bit must be false.
This bit is only defined on Comet Lake, and is reserved MBZ (must be zero)
on all other platforms. This gives us the right read semantics, as the
feature appears disabled on these platforms.
Defined at line 479 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_enhanced_channel_mode (typename SelfType::ValueType val)If true, the channel operates as two 32-bit channels.
This bit must be true in LPDDR4 configurations, and can be set to
true for LPDDR3. In all other configurations, this bit must be false.
This bit is only defined on Comet Lake, and is reserved MBZ (must be zero)
on all other platforms. This gives us the right read semantics, as the
feature appears disabled on these platforms.
Defined at line 479 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >DdrTypeValue ddr_type_select ()The type of DDR memory installed in the system.
Bit 2 only belongs to this field on Comet Lake. On other platforms, bit 2
is reserved MBZ (must be zero). This gives us the right read semantics,
because all documented DDR type values have bit 2 set to zero.
Comet Lake memory controllers use the DDR type values documented here, in
`DdrTypeValue`. This is the main reason we use this class for Comet Lake,
instead of `MemoryAddressDecoderInterChannelConfigIceLake`.
Defined at line 490 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_ddr_type_select (DdrTypeValue val)The type of DDR memory installed in the system.
Bit 2 only belongs to this field on Comet Lake. On other platforms, bit 2
is reserved MBZ (must be zero). This gives us the right read semantics,
because all documented DDR type values have bit 2 set to zero.
Comet Lake memory controllers use the DDR type values documented here, in
`DdrTypeValue`. This is the main reason we use this class for Comet Lake,
instead of `MemoryAddressDecoderInterChannelConfigIceLake`.
Defined at line 490 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
hwreg::RegisterAddr<MemoryAddressDecoderInterChannelConfigSkylake> Get ()Defined at line 492 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
Enumerations
enum DdrTypeValue| Name | Value |
|---|---|
| kDoubleDataRam4 | 0b000 |
| kDoubleDataRam3 | 0b011 |
| kLowPowerDoubleDataRam3 | 0b010 |
| kLowPowerDoubleDataRam4 | 0b011 |
Documented values for `ddr_type_select`.
Defined at line 435 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h