class DataBufferControl
Defined at line 609 of file ../../src/graphics/display/drivers/intel-display/registers.h
DBUF_CTL (DBUF Slice Control)
Some of the register's reserved are not documented as MBZ (must be zero). So,
this register can only be safely updated using read-modify-write operations.
The "Data Buffer" expansion for the DBUF acronym is implicitly documented in
the "Shared Functions" > "Data Buffer" section of the display engine PRMs
(Vol 12 for all recent display engines), which lists all the DBUF-related
registers.
Tiger Lake: IHD-OS-TGL-Vol 2c-12.21 Part 1 pages 331-332
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 1 pages 309-310
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 430-431
Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 1 pages 426-427
Public Members
field_powered_on_target_618 field_powered_on_621 field_maximum_tracker_state_delay_tiger_lake_627 field_maximum_cc_block_valid_delay_633Public Methods
template <, >typename SelfType::ValueType powered_on_target ()The eventual state that `powered_on` will reach.
If true, the DBUF (Data Buffer) slice will eventually power on. If false,
the DBUF slice will eventually power off.
The first DBUF slice must be powered on before using the display engine.
Powering it on is a step in the "Sequences to Initialize Display".
Defined at line 618 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_powered_on_target (typename SelfType::ValueType val)The eventual state that `powered_on` will reach.
If true, the DBUF (Data Buffer) slice will eventually power on. If false,
the DBUF slice will eventually power off.
The first DBUF slice must be powered on before using the display engine.
Powering it on is a step in the "Sequences to Initialize Display".
Defined at line 618 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType powered_on ()If true, the DBUF (Data Buffer) slice is powered on.
Defined at line 621 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_powered_on (typename SelfType::ValueType val)If true, the DBUF (Data Buffer) slice is powered on.
Defined at line 621 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType maximum_tracker_state_delay_tiger_lake ()Maximum number of clock cycles until the tracker state is serviced.
This field is not documented on Kaby Lake and Skylake. The underlying bits
are documented as reserved MBZ (must be zero).
Defined at line 627 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_maximum_tracker_state_delay_tiger_lake (typename SelfType::ValueType val)Maximum number of clock cycles until the tracker state is serviced.
This field is not documented on Kaby Lake and Skylake. The underlying bits
are documented as reserved MBZ (must be zero).
Defined at line 627 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >typename SelfType::ValueType maximum_cc_block_valid_delay ()Maximum number of clock cycles until the CC block valid state is serviced.
This field is not documented on Kaby Lake and Skylake. The underlying bits
are documented as reserved MBZ (must be zero).
Defined at line 633 of file ../../src/graphics/display/drivers/intel-display/registers.h
template <, >SelfType & set_maximum_cc_block_valid_delay (typename SelfType::ValueType val)Maximum number of clock cycles until the CC block valid state is serviced.
This field is not documented on Kaby Lake and Skylake. The underlying bits
are documented as reserved MBZ (must be zero).
Defined at line 633 of file ../../src/graphics/display/drivers/intel-display/registers.h
hwreg::RegisterAddr<DataBufferControl> GetForSlice (int slice_index)DBUF (Data Buffer) slice count varies by display engine.
`slice_index` is 0-based.
Defined at line 638 of file ../../src/graphics/display/drivers/intel-display/registers.h