class DisplayPllControl1
Defined at line 28 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
DPLL_CTRL1 (Display PLL Control 1?)
Some of this register's reserved fields are not MBZ (must be zero). So, the
register can only be updated safely via read-modify-write operations.
This register is not documented on Tiger Lake or DG1.
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 528-531
Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 1 pages 526-529
Public Members
field_RsvdZ_30 field_pll3_uses_hdmi_configuration_mode_44 field_pll3_spread_spectrum_clocking_enabled_45 field_pll3_display_port_ddi_frequency_select_46 field_pll3_programming_enabled_47 field_pll2_uses_hdmi_configuration_mode_49 field_pll2_spread_spectrum_clocking_enabled_50 field_pll2_display_port_ddi_frequency_select_51 field_pll2_programming_enabled_52 field_pll1_uses_hdmi_configuration_mode_54 field_pll1_spread_spectrum_clocking_enabled_55 field_pll1_display_port_ddi_frequency_select_56 field_pll1_programming_enabled_57 field_pll0_display_port_ddi_frequency_select_59 field_pll0_programming_enabled_60Public Methods
template <, >typename SelfType::ValueType pll3_uses_hdmi_configuration_mode ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 44 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll3_uses_hdmi_configuration_mode (typename SelfType::ValueType val)Defined at line 44 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll3_spread_spectrum_clocking_enabled ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 45 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll3_spread_spectrum_clocking_enabled (typename SelfType::ValueType val)Defined at line 45 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >DisplayPortDdiFrequencySelect pll3_display_port_ddi_frequency_select ()Defined at line 46 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll3_display_port_ddi_frequency_select (DisplayPortDdiFrequencySelect val)Defined at line 46 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll3_programming_enabled ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 47 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll3_programming_enabled (typename SelfType::ValueType val)Defined at line 47 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll2_uses_hdmi_configuration_mode ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 49 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll2_uses_hdmi_configuration_mode (typename SelfType::ValueType val)Defined at line 49 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll2_spread_spectrum_clocking_enabled ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 50 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll2_spread_spectrum_clocking_enabled (typename SelfType::ValueType val)Defined at line 50 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >DisplayPortDdiFrequencySelect pll2_display_port_ddi_frequency_select ()Defined at line 51 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll2_display_port_ddi_frequency_select (DisplayPortDdiFrequencySelect val)Defined at line 51 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll2_programming_enabled ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 52 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll2_programming_enabled (typename SelfType::ValueType val)Defined at line 52 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll1_uses_hdmi_configuration_mode ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 54 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll1_uses_hdmi_configuration_mode (typename SelfType::ValueType val)Defined at line 54 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll1_spread_spectrum_clocking_enabled ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 55 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll1_spread_spectrum_clocking_enabled (typename SelfType::ValueType val)Defined at line 55 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >DisplayPortDdiFrequencySelect pll1_display_port_ddi_frequency_select ()Defined at line 56 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll1_display_port_ddi_frequency_select (DisplayPortDdiFrequencySelect val)Defined at line 56 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll1_programming_enabled ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 57 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll1_programming_enabled (typename SelfType::ValueType val)Defined at line 57 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >DisplayPortDdiFrequencySelect pll0_display_port_ddi_frequency_select ()Defined at line 59 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll0_display_port_ddi_frequency_select (DisplayPortDdiFrequencySelect val)Defined at line 59 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll0_programming_enabled ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 60 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll0_programming_enabled (typename SelfType::ValueType val)Defined at line 60 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
bool pll_uses_hdmi_configuration_mode (intel_display::PllId pll_id)If true, the Display PLL is configured for HDMI operation.
If this field is true, the PLL uses the configuration in the DPLL*_CFGCR*
registers. The PLL will generate AFE (Analog Front-End) clock frequencies
suitable for use with DDIs that serve HDMI connections. HDMI operation does
not support SSC (Spread Spectrum Clocking).
If this field is false, the PLL is configured for DisplayPort operation,
which uses the frequency and SSC configuration in this register. The PLL's
AFE clock output frequencies will be suitable for use with DDIs that serve
DisplayPort connections.
This helper always returns false on DPLL0. The underlying field does not
exist for Display PLL0, because PLL0 does not support HDMI operation.
Defined at line 76 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
DisplayPllControl1 & set_pll_uses_hdmi_configuration_mode (intel_display::PllId pll_id, bool hdmi_mode)See `pll_uses_hdmi_configuration_mode()` for details.
Defined at line 91 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
bool pll_spread_spectrum_clocking_enabled (intel_display::PllId pll_id)If true, the Display PLL uses SSC (Spread Spectrum Clocking).
This helper always return false for DPLL (Display PLL) 0. The underlying
field does not exist for DPLL0. DPLL0 does not support SSC, because it must
deliver a constant frequency to the core display clock.
Defined at line 112 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
DisplayPllControl1 & set_pll_spread_spectrum_clocking_enabled (intel_display::PllId pll_id, bool ssc_enabled)See `pll_spread_spectrum_clocking_enabled()` for details.
Defined at line 127 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
int16_t pll_display_port_ddi_frequency_mhz (intel_display::PllId pll_id)The Display PLL's DDI clock frequency, when operating in DisplayPort mode.
This field sets the AFE (Analog Front-End) clock for the DPLL (Display
PLL), when the DPLL is operating in DisplayPort Mode. The AFE clock
dictates the frequency of the DDIs that use this DPLL As their clocking
source.
When a DDI serves a DisplayPort connection, it pushes bits on both clock
edges (rising and falling). So, the AFE clock frequency (which becomes the
DDI's clock frequency) must be set to half the DisplayPort bit rate. For
example, a 2,700 MHz frequency would be used for the HBR2 link rate, which
is 5.4 Gbit/s.
This field is ignored if the DPLL is not operating in DisplayPort mode.
The frequency of DPLL0 indirectly impacts the CDCLK (core display clock)
frequency. The PLL's VCO (voltage-controlled oscillator) frequency will be
either 8,640 Mhz or 8,100 MHz, subject to the constraint that the
DisplayPort frequency must evenly divide the VCO frequency.
This helper returns 0 if the field is set to an undocumented value.
Defined at line 164 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
DisplayPllControl1 & set_pll_display_port_ddi_frequency_mhz (intel_display::PllId pll_id, int16_t ddi_frequency_mhz)See `pll_display_port_ddi_frequency_mhz()` for details.
Defined at line 192 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
bool pll_programming_enabled (intel_display::PllId pll_id)If true, the Display PLL uses the configuration in this register.
Defined at line 230 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
DisplayPllControl1 & set_pll_programming_enabled (intel_display::PllId pll_id, bool programming_enabled)See `pll_programming_enabled()` for details.
Defined at line 241 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
hwreg::RegisterAddr<DisplayPllControl1> Get ()Defined at line 253 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
Enumerations
enum DisplayPortDdiFrequencySelect| Name | Value |
|---|---|
| k2700Mhz | 0b000 |
| k1350Mhz | 0b001 |
| k810Mhz | 0b010 |
| k1620Mhz | 0b011 |
| k1080Mhz | 0b100 |
| k2160Mhz | 0b101 |
Documented values for the `pll_display_port_ddi_frequency_select` fields.
Defined at line 33 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h