class PchPanelPowerControl
Defined at line 235 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
PP_CONTROL (Panel Power Control)
The Tiger Lake PRMS do not include a description for this register. However,
IHD-OS-TGL-Vol 14-12.21 pages 29 and 56 mention the register name and
address. Experiments on Tiger Lake (device ID 0x9a49) suggest that this
register has the same semantics as in DG1.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 pages 961-962
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 2 pages 986-987
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 2 pages 626-627
Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 2 pages 620-621
Public Members
field_power_cycle_delay_243 field_vdd_always_on_260 field_backlight_enabled_263 field_power_down_on_reset_268 field_power_state_target_280Public Methods
template <, >typename SelfType::ValueType power_cycle_delay ()eDP T12 - Required delay from panel power disable to power enable.
Value = (desired_delay / 100ms) + 1.
Zero means no delay, and also stops a current delay.
Must be zero on Kaby Lake and Skylake.
Defined at line 243 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >SelfType & set_power_cycle_delay (typename SelfType::ValueType val)eDP T12 - Required delay from panel power disable to power enable.
Value = (desired_delay / 100ms) + 1.
Zero means no delay, and also stops a current delay.
Must be zero on Kaby Lake and Skylake.
Defined at line 243 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >SelfType & set_vdd_always_on (typename SelfType::ValueType val)If true, the eDP port's VDD is on even if the panel power sequence hasn't
been completed. Intended for panels that need VDD for DP AUX transactions.
This setting overrides all power sequencing logic. So, we (the display
driver) must enforce the eDP T12 power delay. In other words, we must make
sure that that the delay between setting `force` to false and setting it
back to true is at least T12. Additional documentation sources:
* Kaby Lake - IHD-OS-KBL-Vol 16-1.17 page 20
* Skyake - IHD-OS-SKL-Vol 16-05.16 page 9
The Intel documentation references the T4 delay from the SPWG Notebook
Panel Specification 3.8, Section 5.9 "Panel Power Sequence", page 26. The
T4 delay there is equivalent to the T12 delay in the eDP Standard version
1.4b (revised on December 31, 2020), Section 11 "Power Sequencing", pages
249 and 251.
Defined at line 260 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >typename SelfType::ValueType vdd_always_on ()If true, the eDP port's VDD is on even if the panel power sequence hasn't
been completed. Intended for panels that need VDD for DP AUX transactions.
This setting overrides all power sequencing logic. So, we (the display
driver) must enforce the eDP T12 power delay. In other words, we must make
sure that that the delay between setting `force` to false and setting it
back to true is at least T12. Additional documentation sources:
* Kaby Lake - IHD-OS-KBL-Vol 16-1.17 page 20
* Skyake - IHD-OS-SKL-Vol 16-05.16 page 9
The Intel documentation references the T4 delay from the SPWG Notebook
Panel Specification 3.8, Section 5.9 "Panel Power Sequence", page 26. The
T4 delay there is equivalent to the T12 delay in the eDP Standard version
1.4b (revised on December 31, 2020), Section 11 "Power Sequencing", pages
249 and 251.
Defined at line 260 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >typename SelfType::ValueType backlight_enabled ()If true, the backlight is on when the panel is in the powered on state.
Defined at line 263 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >SelfType & set_backlight_enabled (typename SelfType::ValueType val)If true, the backlight is on when the panel is in the powered on state.
Defined at line 263 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >typename SelfType::ValueType power_down_on_reset ()If true, panel runs power down sequence when reset is detected.
Recommended for preserving the panel's lifetime.
Defined at line 268 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >SelfType & set_power_down_on_reset (typename SelfType::ValueType val)If true, panel runs power down sequence when reset is detected.
Recommended for preserving the panel's lifetime.
Defined at line 268 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >typename SelfType::ValueType power_state_target ()If true, the panel will eventually be powered on. This may initiate a panel
power on sequence, which would require waiting for an ongoing power off
sequence to complete, and then honoring the T12 delay.
If false, the panel will eventually be powered off. This may initiate a
power off sequence, which would require waiting for an ongoing power on
sequence to complete, and then honoring the TXX delay.
The panel power on sequence must not be initiated until all panel delays
are set correctly.
Defined at line 280 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
template <, >SelfType & set_power_state_target (typename SelfType::ValueType val)If true, the panel will eventually be powered on. This may initiate a panel
power on sequence, which would require waiting for an ongoing power off
sequence to complete, and then honoring the T12 delay.
If false, the panel will eventually be powered off. This may initiate a
power off sequence, which would require waiting for an ongoing power on
sequence to complete, and then honoring the TXX delay.
The panel power on sequence must not be initiated until all panel delays
are set correctly.
Defined at line 280 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h
hwreg::RegisterAddr<PchPanelPowerControl> Get ()Defined at line 282 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h