struct

If true, the eDP port's VDD is on even if the panel power sequence hasn't

been completed. Intended for panels that need VDD for DP AUX transactions.

This setting overrides all power sequencing logic. So, we (the display

driver) must enforce the eDP T12 power delay. In other words, we must make

sure that that the delay between setting `force` to false and setting it

back to true is at least T12. Additional documentation sources:

* Kaby Lake - IHD-OS-KBL-Vol 16-1.17 page 20

* Skyake - IHD-OS-SKL-Vol 16-05.16 page 9

The Intel documentation references the T4 delay from the SPWG Notebook

Panel Specification 3.8, Section 5.9 "Panel Power Sequence", page 26. The

T4 delay there is equivalent to the T12 delay in the eDP Standard version

1.4b (revised on December 31, 2020), Section 11 "Power Sequencing", pages

249 and 251.