class PortTransmitterMipiEqualization

Defined at line 776 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

PORT_TX_DW0 (Transmitter analog front-end config double-word 0?)

This register controls transmitter equalization in the Combo PHY's AFE

(Analog Front-End).

All reserved bits in this register are MBZ (must be zero). So, the register

can be safely updated without reading it first.

This register is not documented on Kaby Lake or Skylake.

Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 pages 929-931

DG1: IHD-OS-DG1-Vol 2c-2.21 Part 2 pages 945-948

Public Members

 field_mipi_equalization_is_high_784

 field_mipi_equalization_enabled_789

 field_post_cursor_coefficient_794

 field_mipi_equalization_override_801

 field_RsvdZ_803

 field_cursor_coefficient_808

Public Methods

template <, >

typename SelfType::ValueType mipi_equalization_is_high ()

Selects the equalization level for MIPI DSI transmission.

This bit is ignored unless `mipi_equalization_override` is true.

Low level equalization is 3.5 dB. High level equalization is 7 dB.

Defined at line 784 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

SelfType & set_mipi_equalization_is_high (typename SelfType::ValueType val)

Selects the equalization level for MIPI DSI transmission.

This bit is ignored unless `mipi_equalization_override` is true.

Low level equalization is 3.5 dB. High level equalization is 7 dB.

Defined at line 784 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

typename SelfType::ValueType mipi_equalization_enabled ()

If true, lane equalization for MIPI DSI transmission is enabled.

This bit is ignored unless `mipi_equalization_override` is true.

Defined at line 789 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

SelfType & set_mipi_equalization_enabled (typename SelfType::ValueType val)

If true, lane equalization for MIPI DSI transmission is enabled.

This bit is ignored unless `mipi_equalization_override` is true.

Defined at line 789 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

typename SelfType::ValueType post_cursor_coefficient ()

Transmitter equalization tap C+1 (post-cursor) coefficient.

The PRM advises against changing this field. The default value is 0xb.

Defined at line 794 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

SelfType & set_post_cursor_coefficient (typename SelfType::ValueType val)

Transmitter equalization tap C+1 (post-cursor) coefficient.

The PRM advises against changing this field. The default value is 0xb.

Defined at line 794 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

typename SelfType::ValueType mipi_equalization_override ()

If true, the equalization logic is driven by fields in this register.

If this field is false, the equalization logic is driven by PPI (PHY

Protocol Interface, in the MIPI D-PHY specification) Transmitter

Equalization pins (TxEqActiveHS, TxEqLevelHS).

Defined at line 801 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

SelfType & set_mipi_equalization_override (typename SelfType::ValueType val)

If true, the equalization logic is driven by fields in this register.

If this field is false, the equalization logic is driven by PPI (PHY

Protocol Interface, in the MIPI D-PHY specification) Transmitter

Equalization pins (TxEqActiveHS, TxEqLevelHS).

Defined at line 801 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

typename SelfType::ValueType cursor_coefficient ()

Transmitter equalization tap C (cursor) coefficient.

The PRM advises against changing this field. The default value is 0x34.

Defined at line 808 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

template <, >

SelfType & set_cursor_coefficient (typename SelfType::ValueType val)

Transmitter equalization tap C (cursor) coefficient.

The PRM advises against changing this field. The default value is 0x34.

Defined at line 808 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

hwreg::RegisterAddr<PortTransmitterMipiEqualization> GetForDdiLane (intel_display::DdiId ddi_id, PortLane lane)

Defined at line 810 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h

uint32_t MmioAddressForDdiLane (intel_display::DdiId ddi_id, PortLane lane)

Returns the base address of lane's PORT_TX_ configuration registers.

Defined at line 816 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h