class DynamicFlexIoDisplayPortMainLinkLaneEnabled

class DynamicFlexIoDisplayPortMainLinkLaneEnabled

Defined at line 69 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

PORT_TX_DFLEXDPMLE1

Dynamic FlexIO DisplayPort Main-Link Lane Enable 1 (for Type-C Connector 0-7)

(?)

This FIA register is used for drivers to tell FIA hardware which main link

lanes of DisplayPort are enabled on each Type-C connector.

Notes:

1. The connector ID here is the logical number for each FIA, and the Type-C

port to FIA connector ID mapping is available at:

Tiger Lake: IHD-OS-TGL-Vol 12-1.22-Rev2.0 "TypeC Programming" > "Port

Mapping" table, Page 400.

2. The display driver may only change this register when the DisplayPort

controller is in safe mode (see

`DynamicFlexIoDisplayPortControllerSafeStateSettings`).

3. Intel Graphics Programmer's reference manual (register definitions, and

display engine) also uses "main links" in this register's definition to

refer to the DisplayPort main-link lanes (also known as "DisplayPort lanes").

Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev 2.0 Part 2, Pages 913-915.

Public Members

Public Methods

template <, >
typename SelfType::ValueType connector_1_display_port_main_link_lane_3_enabled ()

Indicates whether DisplayPort Main link lane 3 (ML3) is enabled on

connector 1.

Drivers can use helper method `enabled_main_links_bits`,

`set_enabled_main_links_bits` to get / set main link status bitmap for a

given DDI.

The register has these bit fields for Connector 0 to 7. Since on Tiger

Lake each FIA only connects to two connectors, we only define the bits for

connector 0 and 1.

Defined at line 82 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_1_display_port_main_link_lane_3_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 3 (ML3) is enabled on

connector 1.

Drivers can use helper method `enabled_main_links_bits`,

`set_enabled_main_links_bits` to get / set main link status bitmap for a

given DDI.

The register has these bit fields for Connector 0 to 7. Since on Tiger

Lake each FIA only connects to two connectors, we only define the bits for

connector 0 and 1.

Defined at line 82 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
typename SelfType::ValueType connector_1_display_port_main_link_lane_2_enabled ()

Indicates whether DisplayPort Main link lane 2 (ML2) is enabled on

connector 1.

Defined at line 86 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_1_display_port_main_link_lane_2_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 2 (ML2) is enabled on

connector 1.

Defined at line 86 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
typename SelfType::ValueType connector_1_display_port_main_link_lane_1_enabled ()

Indicates whether DisplayPort Main link lane 1 (ML1) is enabled on

connector 1.

Defined at line 90 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_1_display_port_main_link_lane_1_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 1 (ML1) is enabled on

connector 1.

Defined at line 90 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
typename SelfType::ValueType connector_1_display_port_main_link_lane_0_enabled ()

Indicates whether DisplayPort Main link lane 0 (ML0) is enabled on

connector 1.

Defined at line 94 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_1_display_port_main_link_lane_0_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 0 (ML0) is enabled on

connector 1.

Defined at line 94 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
typename SelfType::ValueType connector_0_display_port_main_link_lane_3_enabled ()

Indicates whether DisplayPort Main link lane 3 (ML3) is enabled on

connector 0.

Defined at line 98 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_0_display_port_main_link_lane_3_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 3 (ML3) is enabled on

connector 0.

Defined at line 98 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
typename SelfType::ValueType connector_0_display_port_main_link_lane_2_enabled ()

Indicates whether DisplayPort Main link lane 2 (ML2) is enabled on

connector 0.

Defined at line 102 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_0_display_port_main_link_lane_2_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 2 (ML2) is enabled on

connector 0.

Defined at line 102 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
typename SelfType::ValueType connector_0_display_port_main_link_lane_1_enabled ()

Indicates whether DisplayPort Main link lane 1 (ML1) is enabled on

connector 0.

Defined at line 106 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_0_display_port_main_link_lane_1_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 1 (ML1) is enabled on

connector 0.

Defined at line 106 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
typename SelfType::ValueType connector_0_display_port_main_link_lane_0_enabled ()

Indicates whether DisplayPort Main link lane 0 (ML0) is enabled on

connector 0.

Defined at line 110 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

template <, >
SelfType & set_connector_0_display_port_main_link_lane_0_enabled (typename SelfType::ValueType val)

Indicates whether DisplayPort Main link lane 0 (ML0) is enabled on

connector 0.

Defined at line 110 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

uint32_t enabled_display_port_main_link_lane_bits (intel_display::DdiId ddi_id)

Getter of `connector_1_display_port_main_link_lane_{0,1,2,3}_enabled` and

`connector_0_display_port_main_link_lane_{0,1,2,3}_enabled` fields above

based on `ddi_id`.

Callers must make sure they read from the correct FIA register.

Defined at line 117 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

SelfType & set_enabled_display_port_main_link_lane_bits (intel_display::DdiId ddi_id, uint32_t bits)

Setter of `connector_1_display_port_main_link_lane_{0,1,2,3}_enabled` and

`connector_0_display_port_main_link_lane_{0,1,2,3}_enabled` fields above

based on `ddi_id`.

Callers must make sure they write to the correct FIA register.

Defined at line 128 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

hwreg::RegisterAddr<SelfType> GetForDdi (intel_display::DdiId ddi_id)

Defined at line 142 of file ../../src/graphics/display/drivers/intel-display/registers-typec.h

Records