class GMBusCommand

This bit is used to clear error flags and resets the controller status.

For normal bus operation, this bit must be set to 0.

To perform a GMBUS reset,

- Software transitions this bit 0->1 to start the hardware reset sequence.

The GMBUS configuration registers become write-protected.

- Hardware sets the `is_ready` bit in the `GMBusControllerStatus` (GMBUS2)

register to 1 when the reset is complete.

- Software transitions this bit 1->0 to remove the write protection from

the GMBUS configuration registers.

- Hardware sets the `is_ready` bit back to 0 and restores normal operation.

GMBUS can be used.

This bit is used to clear error flags and resets the controller status.

For normal bus operation, this bit must be set to 0.

To perform a GMBUS reset,

- Software transitions this bit 0->1 to start the hardware reset sequence.

The GMBUS configuration registers become write-protected.

- Hardware sets the `is_ready` bit in the `GMBusControllerStatus` (GMBUS2)

register to 1 when the reset is complete.

- Software transitions this bit 1->0 to remove the write protection from

the GMBUS configuration registers.

- Hardware sets the `is_ready` bit back to 0 and restores normal operation.

GMBUS can be used.

Trigger the start of a GMBUS transfer cycle when set to 1.

When `is_ready` in `GMBusControllerStatus` is true and `software_ready`

is 0, the driver can request the GMBUS controller to start handshaking

and data transfer by setting `software_ready` to 1.

Then the `controller_is_ready` bit in `GMBusControllerStatus` (GMBUS2) register will be

de-asserted until GMBUS finishes reading / writing the data register (GMBUS3) or an active

GMBUS cycle is terminated. That will also set `software_ready` bit to 0.

For each transfer, the driver only needs to set `software_ready` bit to 1

once and should not set it again once it's de-asserted.

Trigger the start of a GMBUS transfer cycle when set to 1.

When `is_ready` in `GMBusControllerStatus` is true and `software_ready`

is 0, the driver can request the GMBUS controller to start handshaking

and data transfer by setting `software_ready` to 1.

Then the `controller_is_ready` bit in `GMBusControllerStatus` (GMBUS2) register will be

de-asserted until GMBUS finishes reading / writing the data register (GMBUS3) or an active

GMBUS cycle is terminated. That will also set `software_ready` bit to 0.

For each transfer, the driver only needs to set `software_ready` bit to 1

once and should not set it again once it's de-asserted.

If true, target stall status bit in `GMBusControllerStatus` will be updated

and interrupts will be generated when corresponding mask bit is enabled,

when the target device stalls the acknowledgement bit longer than the time

limit specified (in VESA DDC/CI standard, the required time limit is 2

milliseconds).

If true, target stall status bit in `GMBusControllerStatus` will be updated

and interrupts will be generated when corresponding mask bit is enabled,

when the target device stalls the acknowledgement bit longer than the time

limit specified (in VESA DDC/CI standard, the required time limit is 2

milliseconds).

If true, an I2C STOP signal will be transmitted at the current GMBUS cycle

to terminate the transaction.

Setting this to false while setting `wait_state_enabled` to true allows the

driver to continue data read / write by letting controller issue a RESTART

signal to start a new data cycle after the current GMBUS cycle completes.

If true, an I2C STOP signal will be transmitted at the current GMBUS cycle

to terminate the transaction.

Setting this to false while setting `wait_state_enabled` to true allows the

driver to continue data read / write by letting controller issue a RESTART

signal to start a new data cycle after the current GMBUS cycle completes.

If true, the GMBUS cycle contains a special index write transaction.

When this field is true, the GMBUS controller uses the I2C combined format

to perform a 1-byte or 2-byte index write transaction, immediately followed

(via RESTART) by a second transaction in the direction indicated by

`is_read_transaction`. In other words, the main transaction is preceded

by a short (1-byte / 2-byte) write transaction.

This operation matches the VESA E-DDC (Enhanced Display Data Channel)

specification for reading EDID / DisplayID contents, where the E-DDC

"start address" / "word offset" (0 or 128) is a 1-byte index.

If this field is true, `wait_state_enabled` must also be true.

If true, the GMBUS cycle contains a special index write transaction.

When this field is true, the GMBUS controller uses the I2C combined format

to perform a 1-byte or 2-byte index write transaction, immediately followed

(via RESTART) by a second transaction in the direction indicated by

`is_read_transaction`. In other words, the main transaction is preceded

by a short (1-byte / 2-byte) write transaction.

This operation matches the VESA E-DDC (Enhanced Display Data Channel)

specification for reading EDID / DisplayID contents, where the E-DDC

"start address" / "word offset" (0 or 128) is a 1-byte index.

If this field is true, `wait_state_enabled` must also be true.

If true, the GMBUS controller may enter the wait state after the cycle.

If this field is true and `stop_generated` is false, the GMBUS controller

will enter the wait state after completing the GMBUS cycle, waiting for

the driver to read / write the GMBusData register with new data bytes.

During this state, the GMBUS controller pulls the I2C clock line low to

hold incoming transactions from target devices.

If true, the GMBUS controller may enter the wait state after the cycle.

If this field is true and `stop_generated` is false, the GMBUS controller

will enter the wait state after completing the GMBUS cycle, waiting for

the driver to read / write the GMBusData register with new data bytes.

During this state, the GMBUS controller pulls the I2C clock line low to

hold incoming transactions from target devices.

Total number of bytes to be transferred (read / written) during the DATA

phase of the GMBUS cycle.

The GMBUS controller is expected to read / write `total_byte_count` from

the bus, but this may be prematurely terminated by the driver (by

triggering a STOP cycle) if needed (for example, if the display engine

receives a NACK from the display device).

This field must not be changed once a cycle transaction has started.

The value of this field must not be zero.

Total number of bytes to be transferred (read / written) during the DATA

phase of the GMBUS cycle.

The GMBUS controller is expected to read / write `total_byte_count` from

the bus, but this may be prematurely terminated by the driver (by

triggering a STOP cycle) if needed (for example, if the display engine

receives a NACK from the display device).

This field must not be changed once a cycle transaction has started.

The value of this field must not be zero.

When `index_transaction_used` is set, the index byte in this field will be

written to the `target_address` before the DATA read / write phase.

This field is in effect only when `index_transaction_used` is set, and

`two_byte_index_enable` in GMBusTwoByteIndex (GMBUS5) is disabled.

When `index_transaction_used` is set, the index byte in this field will be

written to the `target_address` before the DATA read / write phase.

This field is in effect only when `index_transaction_used` is set, and

`two_byte_index_enable` in GMBusTwoByteIndex (GMBUS5) is disabled.

7-bit GMBUS target address (SADDR). This is the target address used in I2C

protocol when GMBUS generates bus cycles.

On some documents (including VESA E-DDC and DDC/CI, and Intel Programmer's

Reference Manuals), an 8-bit address is used including this field and the

`is_read_transaction` bit.

Some of the `target_address` / `is_read_transaction` combinations are

reserved by I2C and recognized by GMBUS controller for special purposes,

though the VESA DDC/CI protocol doesn't use or prohibits them.

7-bit GMBUS target address (SADDR). This is the target address used in I2C

protocol when GMBUS generates bus cycles.

On some documents (including VESA E-DDC and DDC/CI, and Intel Programmer's

Reference Manuals), an 8-bit address is used including this field and the

`is_read_transaction` bit.

Some of the `target_address` / `is_read_transaction` combinations are

reserved by I2C and recognized by GMBUS controller for special purposes,

though the VESA DDC/CI protocol doesn't use or prohibits them.

True if the new GMBUS cycle to generate will read data from target device;

otherwise the new cycle will write data to target device.

On some documents, this bit together with `target_address` are combined as

an 8-bit address for target addressing.

True if the new GMBUS cycle to generate will read data from target device;

otherwise the new cycle will write data to target device.

On some documents, this bit together with `target_address` are combined as

an 8-bit address for target addressing.