class DdiBufferControl

If true, the DDI buffer is enabled.

If true, the DDI buffer is enabled.

If true, the DDI ignores PHY parameter changes during link training.

The impacted PHY parameters include voltage swing and pre-emphasis. This

field is generally set when using specific PHY parameters for the DDI.

This field does not exist (is reserved) on Kaby Lake and Skylake.

If true, the DDI ignores PHY parameter changes during link training.

The impacted PHY parameters include voltage swing and pre-emphasis. This

field is generally set when using specific PHY parameters for the DDI.

This field does not exist (is reserved) on Kaby Lake and Skylake.

If true, the DDI uses adjusted PHY parameter values.

The value is ignored if `override_training` is false.

This field does not exist (is reserved) on Kaby Lake and Skylake.

If true, the DDI uses adjusted PHY parameter values.

The value is ignored if `override_training` is false.

This field does not exist (is reserved) on Kaby Lake and Skylake.

Selects one of the DisplayPort PHY configurations set up in DDI_BUF_TRANS.

DDIs A and E support indexes 0 through 9. DDIs B-D only support indexes 0

through 8, because the 9th PHY configuration is used for HDMI.

This field is meaningless for HDMI and DVI.

This field does not exist (is reserved) on Tiger Lake and DG1.

Selects one of the DisplayPort PHY configurations set up in DDI_BUF_TRANS.

DDIs A and E support indexes 0 through 9. DDIs B-D only support indexes 0

through 8, because the 9th PHY configuration is used for HDMI.

This field is meaningless for HDMI and DVI.

This field does not exist (is reserved) on Tiger Lake and DG1.

If true, data is swapped on the lanes output by the port.

This field must not be changed while the DDI is enabled.

Tiger Lake and DG1:

FIA handles lane reversal for Thunderbolt and USB-C DisplayPort Alt Mode,

and this field should be set to false in those cases. Static and fixed

connections (DisplayPort, HDMI) through the FIA only use this field in

"No pin Assignment (Non Type-C DP)" static configurations. Other

connections use the field.

Kaby Lake and Skylake:

For DDIs B-D, enabling swaps lanes 0

<

-> 3 and lanes 1

<

-> 2. If DDI E is

enabled (in DDI A Lane Capability Control), then DDI A reversal swaps its

two remaining lanes (0

<

-> 1). If DDI E is disabled, DDI A reversal acts

the same as B-D reversal (lanes 0

<

-> 3 and 1

<

->2 are swapped). DDI E does

not support port reversal.

If true, data is swapped on the lanes output by the port.

This field must not be changed while the DDI is enabled.

Tiger Lake and DG1:

FIA handles lane reversal for Thunderbolt and USB-C DisplayPort Alt Mode,

and this field should be set to false in those cases. Static and fixed

connections (DisplayPort, HDMI) through the FIA only use this field in

"No pin Assignment (Non Type-C DP)" static configurations. Other

connections use the field.

Kaby Lake and Skylake:

For DDIs B-D, enabling swaps lanes 0

<

-> 3 and lanes 1

<

-> 2. If DDI E is

enabled (in DDI A Lane Capability Control), then DDI A reversal swaps its

two remaining lanes (0

<

-> 1). If DDI E is disabled, DDI A reversal acts

the same as B-D reversal (lanes 0

<

-> 3 and 1

<

->2 are swapped). DDI E does

not support port reversal.

Delay used to stagger the assertion/deassertion of the port lane enables.

The value is expressed in multiples of the symbol clock period, so it

depends on the link frequency.

The delay should be at least 100ns when the port is used in USB Type C

mode. In all other cases, the delay should be zero.

This field does not exist (is reserved) on Kaby Lake and Skylake, which

don't have Type C DDIs.

Delay used to stagger the assertion/deassertion of the port lane enables.

The value is expressed in multiples of the symbol clock period, so it

depends on the link frequency.

The delay should be at least 100ns when the port is used in USB Type C

mode. In all other cases, the delay should be zero.

This field does not exist (is reserved) on Kaby Lake and Skylake, which

don't have Type C DDIs.

If true, the DDI is idle.

If true, the DDI is idle.

If false, two lanes from DDI A are repurposed to form DDI E.

If true, DDI A has four lanes, and behaves similarly to DDIs B-D. If false,

This field is only meaningful on DDI A, whose lanes get redistributed to

DDI E. The field must be programmed at boot time (based on the board

configuration) and must not be changed afterwards.

This field does not exist (is reserved) on Tiger Lake or DG1.

If false, two lanes from DDI A are repurposed to form DDI E.

If true, DDI A has four lanes, and behaves similarly to DDIs B-D. If false,

This field is only meaningful on DDI A, whose lanes get redistributed to

DDI E. The field must be programmed at boot time (based on the board

configuration) and must not be changed afterwards.

This field does not exist (is reserved) on Tiger Lake or DG1.

Selects the number of DisplayPort lanes enabled.

The field's value is the number of lanes minus 1. 0 = x1 lane, 1 = x2

lanes, 3 = x4 lanes. display_port_lane_count() and

set_display_port_lane_count() take care of this encoding detail.

Selects the number of DisplayPort lanes enabled.

The field's value is the number of lanes minus 1. 0 = x1 lane, 1 = x2

lanes, 3 = x4 lanes. display_port_lane_count() and

set_display_port_lane_count() take care of this encoding detail.

The number of DisplayPort lanes enabled.

This field is not meaningful for HDMI, which always uses all the lanes.

When the DDI is in DisplayPort mode, the field must match the corresponding

setting in TRANS_DDI_FUNC_CTL for the transcoder attached to this DDI.

On Kaby Lake and Skylake, DDI E only supports 1 and 2 lanes

(if it's enabled), since it takes two lanes from DDI A. On the same

hardware, DDI A always supports x1 and x2, and supports x4 if DDI E is

disabled (and therefore not taking away 2 lanes from DDI A).

See display_port_lane_count() for details.

The level of the port detect pin at boot time.

This field is only meaningful on DDI A. On Skylake and Kaby Lake, the other

DDIs' port detect pin status is communicated in SFUSE_STRAP.

The level of the port detect pin at boot time.

This field is only meaningful on DDI A. On Skylake and Kaby Lake, the other

DDIs' port detect pin status is communicated in SFUSE_STRAP.

For Kaby Lake and Skylake DDI A - DDI E.

For Tiger Lake and DG1.