class PortCommonLaneMainLinkPower
Defined at line 150 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
PORT_CL_DW10 (PHY Common Lane config double-word 10?)
This register has bits that are reserved but not MBZ (must be zero). So, it
can only be safely updated via read-modify-write operations.
This register is not documented on Kaby Lake or Skylake.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 pages 887-889
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 2 pages 899-901
Ice Lake: IHD-OS-ICLLP-Vol 2c-1.22-Rev2.0 Part 2 pages 555-556
Public Members
field_RsvdZ_159 field_power_gate_sequential_delay_override_161 field_power_gate_sequential_delay_override_valid_164 field_high_voltage_power_gate_control_172 field_high_voltage_power_gate_control_dsi_c_178 field_common_register_interface_ret_181 field_RsvdZ_183 field_power_down_lane3_189 field_power_down_lane2_195 field_power_down_lane1_201 field_power_down_lane0_207 field_edp_power_optimized_mode_valid_213 field_edp_power_optimized_mode_enabled_219 field_terminating_resistor_override_valid_222 field_terminating_resistor_override_225Public Methods
template <, >typename SelfType::ValueType power_gate_sequential_delay_override ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 161 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_power_gate_sequential_delay_override (typename SelfType::ValueType val)Defined at line 161 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType power_gate_sequential_delay_override_valid ()If false, `power_gate_sequential_delay_override` is ignored.
Defined at line 164 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_power_gate_sequential_delay_override_valid (typename SelfType::ValueType val)If false, `power_gate_sequential_delay_override` is ignored.
Defined at line 164 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType high_voltage_power_gate_control ()HPVG (High Voltage Power Gate) for the MIPI DSI operating mode.
On Ice Lake display engines with one common lane for all IOs, this bit
controls the HVPG (High-Voltage Power Gate) for DSI0 (MIPI A).
On display engines without MIPI DSI support, this bit is ignored.
Defined at line 172 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_high_voltage_power_gate_control (typename SelfType::ValueType val)HPVG (High Voltage Power Gate) for the MIPI DSI operating mode.
On Ice Lake display engines with one common lane for all IOs, this bit
controls the HVPG (High-Voltage Power Gate) for DSI0 (MIPI A).
On display engines without MIPI DSI support, this bit is ignored.
Defined at line 172 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType high_voltage_power_gate_control_dsi_c ()Unused (Common Register Interface spare bit) on most display engines.
On Ice Lake display engines with one common lane for all IOs, this bit
controls the HVPG (High-Voltage Power Gate) for DSI1 (MIPI C).
Defined at line 178 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_high_voltage_power_gate_control_dsi_c (typename SelfType::ValueType val)Unused (Common Register Interface spare bit) on most display engines.
On Ice Lake display engines with one common lane for all IOs, this bit
controls the HVPG (High-Voltage Power Gate) for DSI1 (MIPI C).
Defined at line 178 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType common_register_interface_ret ()CRI (Common Register Interface) spare bits.
Defined at line 181 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_common_register_interface_ret (typename SelfType::ValueType val)CRI (Common Register Interface) spare bits.
Defined at line 181 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType power_down_lane3 ()If true, the DDI's main link lane 3 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 189 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_power_down_lane3 (typename SelfType::ValueType val)If true, the DDI's main link lane 3 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 189 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType power_down_lane2 ()If true, the DDI's main link lane 2 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 195 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_power_down_lane2 (typename SelfType::ValueType val)If true, the DDI's main link lane 2 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 195 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType power_down_lane1 ()If true, the DDI's main link lane 1 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 201 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_power_down_lane1 (typename SelfType::ValueType val)If true, the DDI's main link lane 1 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 201 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType power_down_lane0 ()If true, the DDI's main link lane 0 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 207 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_power_down_lane0 (typename SelfType::ValueType val)If true, the DDI's main link lane 0 is powered down.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 207 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType edp_power_optimized_mode_valid ()If false, `edp_power_optimized_mode_enabled` is ignored.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 213 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_edp_power_optimized_mode_valid (typename SelfType::ValueType val)If false, `edp_power_optimized_mode_enabled` is ignored.
Some `power_down_lane*` field combinations are not supported. The
`set_powered_up_lanes()` helper is guaranteed to set valid combinations.
Defined at line 213 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType edp_power_optimized_mode_enabled ()If true, enables a eDP (embedded DisplayPort) power-optimized mode.
This field is ignored if `edp_power_optimized_mode_valid` is false. Setting
this to true must be accompanied by a specific voltage swing configuration.
Defined at line 219 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_edp_power_optimized_mode_enabled (typename SelfType::ValueType val)If true, enables a eDP (embedded DisplayPort) power-optimized mode.
This field is ignored if `edp_power_optimized_mode_valid` is false. Setting
this to true must be accompanied by a specific voltage swing configuration.
Defined at line 219 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_terminating_resistor_override_valid (typename SelfType::ValueType val)If false, `terminating_resistor_override` is ignored.
Defined at line 222 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType terminating_resistor_override_valid ()If false, `terminating_resistor_override` is ignored.
Defined at line 222 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_terminating_resistor_override (TerminatingResistorOverride val)Overrides the terminating resisor value.
Defined at line 225 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >TerminatingResistorOverride terminating_resistor_override ()Overrides the terminating resisor value.
Defined at line 225 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
PortCommonLaneMainLinkPower & set_powered_up_lanes (int active_lane_count)Powers up/down DDI main link lanes.
`active_lane_count` must be a 1/2/4 for DisplayPort connections, and 4 for
HDMI connections. DSI connections are not currently supported.
Defined at line 231 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
PortCommonLaneMainLinkPower & set_powered_up_lanes_reversed (int active_lane_count)Powers up/down DDI main link lanes for a reverse connection.
`active_lane_count` must be a 1/2/4 for DisplayPort connections, and 4 for
HDMI connections. DSI connections are not currently supported.
Defined at line 244 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
hwreg::RegisterAddr<PortCommonLaneMainLinkPower> GetForDdi (intel_display::DdiId ddi_id)Defined at line 253 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
Enumerations
enum TerminatingResistorOverride| Name | Value |
|---|---|
| k150Ohms | 0 |
| k100Ohms | 1 |
Possible values for the `terminating_resistor_override` field.
Defined at line 154 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h