class PchChicken1

Defined at line 140 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

SCHICKEN_1 (South / PCH Display Engine Chicken 1)

This register is not explicitly documented, but the Kaby Lake PRMs have clues

that reveal its name and address.

* IHD-OS-KBL-Vol 2c-1.17 Part 2 page 788 mentions the SCHICKEN_1 name, and

that bit 0 selects between a multiplier of 16 and 128 for SBLC_PWM_CTL2

backlight modulation and duty cycle.

* IHD-OS-KBL-Vol 12-1.17 "Backlight Enabling Sequence" page 197 states that

a granularity of 16 or 128 is set in bit 0 of the 0xC2000 register.

The name is a reference to "chicken bits", which are configuration bits that

create the option to reverse (chicken out of) risky design changes (fixes or

new features). The risk can be due to the complexity of the feature, or due

to having to make changes late in the design cycle. More details in

"Formal Verification - An Essential Toolkit for Modern VLSI Design".

Public Members

 field_hpd_invert_bits_150

 field_pch_display_clock_disable_162

 field_genlock_instead_of_backlight_169

 field_backlight_pwm_multiplier_182

Public Methods

template <, >

typename SelfType::ValueType hpd_invert_bits ()

All bits must be set to 1 on DG1.

Setting the bits to 1 compensates for the fact that DG1's HPD signals are

inverted (0 = connected, 1 = disconnected). This issue is not mentioned in

other PRMs.

DG1: IHD-OS-DG1-Vol 12-2.21 "Hotplug Board Inversion" page 352 and

IHD-OS-DG1-Vol 2c-2.21 Part 2 page 1259

Defined at line 150 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_hpd_invert_bits (typename SelfType::ValueType val)

All bits must be set to 1 on DG1.

Setting the bits to 1 compensates for the fact that DG1's HPD signals are

inverted (0 = connected, 1 = disconnected). This issue is not mentioned in

other PRMs.

DG1: IHD-OS-DG1-Vol 12-2.21 "Hotplug Board Inversion" page 352 and

IHD-OS-DG1-Vol 2c-2.21 Part 2 page 1259

Defined at line 150 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

typename SelfType::ValueType pch_display_clock_disable ()

Set on S0ix entry and cleared on S0ix exit.

This bit works around an issue bug where the PCH display engine's clock

is not stopped when entering the S0ix state. This issue is mentioned in the

PRMs listed below.

Lakefield: IHD-OS-LKF-Vol 14-4.21 page 15

Tiger Lake: IHD-OS-TGL-Vol 14-12.21 page 18 and page 50

Ice Lake: IHD-OS-ICLLP-Vol 14-1.20 page 33

Not mentioned in DG1, Kaby Lake, or Skylake.

Defined at line 162 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_pch_display_clock_disable (typename SelfType::ValueType val)

Set on S0ix entry and cleared on S0ix exit.

This bit works around an issue bug where the PCH display engine's clock

is not stopped when entering the S0ix state. This issue is mentioned in the

PRMs listed below.

Lakefield: IHD-OS-LKF-Vol 14-4.21 page 15

Tiger Lake: IHD-OS-TGL-Vol 14-12.21 page 18 and page 50

Ice Lake: IHD-OS-ICLLP-Vol 14-1.20 page 33

Not mentioned in DG1, Kaby Lake, or Skylake.

Defined at line 162 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

typename SelfType::ValueType genlock_instead_of_backlight ()

Toggles shared IO pins between multi-chip genlock and backlight 2.

Lake Field: IHD-OS-LKF-Vol 12-4.21 page 50

DG1: IHD-OS-DG1-Vol 12-2.21 page 349

Kaby Lake and Skylake don't support multi-chip genlock.

Defined at line 169 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_genlock_instead_of_backlight (typename SelfType::ValueType val)

Toggles shared IO pins between multi-chip genlock and backlight 2.

Lake Field: IHD-OS-LKF-Vol 12-4.21 page 50

DG1: IHD-OS-DG1-Vol 12-2.21 page 349

Kaby Lake and Skylake don't support multi-chip genlock.

Defined at line 169 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

typename SelfType::ValueType backlight_pwm_multiplier ()

Multiplier for the backlight PWM frequency and duty cycle.

This multiplier applies to SBLC_PWM_CTL1 and SBLC_PWM_CTL2. It is not

present on DG1, where the PWM frequency and duty cycle are specified as

32-bit values in the SBLC_PWM_FREQ and SBLC_PWM_DUTY registers.

The multiplier can be 16 (0) or 128 (1).

Kaby Lake: IHD-OS-KBL-Vol 12-1.17 "Backlight Enabling Sequence" page 197

Skylake: IHD-OS-SKL-Vol 12-05.16 "Backlight Enabling Sequence" page 189

Does not exist on DG1.

Defined at line 182 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_backlight_pwm_multiplier (typename SelfType::ValueType val)