class PchPanelPowerClockDelay

Defined at line 294 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

PP_DIVISOR (Panel Power Cycle Delay and Reference Divisor)

On Tiger Lake and DG1, the T12 value is stored in PP_CONTROL, and there is no

documented register for setting the panel clock divisor.

Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 2 page 629

Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 2 page 623

Public Members

 field_clock_divider_303

 field_power_cycle_delay_311

template <, >

typename SelfType::ValueType clock_divider ()

Divider that generates the panel power clock from the PCH raw clock.

Value = divider / 2 - 1. 0 is not a valid value.

Intel's PRMs state that the panel clock must always be 10 kHz. This results

in a 100us period, which is assumed to be the base unit for all panel

timings.

Defined at line 303 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_clock_divider (typename SelfType::ValueType val)

Divider that generates the panel power clock from the PCH raw clock.

Value = divider / 2 - 1. 0 is not a valid value.

Intel's PRMs state that the panel clock must always be 10 kHz. This results

in a 100us period, which is assumed to be the base unit for all panel

timings.

Defined at line 303 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

typename SelfType::ValueType power_cycle_delay ()

eDP T12 - Required delay from panel power disable to power enable.

Value = (desired_delay / 100ms) + 1.

Zero means no delay, and also stops a current delay.

This field is stored in PP_CONTROL on DG1.

Defined at line 311 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_power_cycle_delay (typename SelfType::ValueType val)

eDP T12 - Required delay from panel power disable to power enable.

Value = (desired_delay / 100ms) + 1.

Zero means no delay, and also stops a current delay.

This field is stored in PP_CONTROL on DG1.

Defined at line 311 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

hwreg::RegisterAddr<PchPanelPowerClockDelay> Get ()

Defined at line 313 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h