class PortTransmitterEqualization
Defined at line 937 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
PORT_TX_DW4 (Transmitter analog front-end config double-word 4?)
This register has bits that are reserved but not MBZ (must be zero). So, it
can only be safely updated via read-modify-write operations.
This register is not documented on Kaby Lake or Skylake.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 pages 938-940
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 2 pages 957-960
Ice Lake: IHD-OS-ICLLP-Vol 2c-1.22-Rev2.0 Part 2 pages 618-620
Public Members
field_load_generation_select_940 field_bs_comp_override_942 field_termination_resistance_limit_944 field_post_cursor_coefficient1_947 field_post_cursor_coefficient2_950 field_cursor_coefficient_953Public Methods
template <, >typename SelfType::ValueType load_generation_select ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 940 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_load_generation_select (typename SelfType::ValueType val)Defined at line 940 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType bs_comp_override ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 942 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_bs_comp_override (typename SelfType::ValueType val)Defined at line 942 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_termination_resistance_limit (typename SelfType::ValueType val)Defined at line 944 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType termination_resistance_limit ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 944 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType post_cursor_coefficient1 ()Equalization tap C+1 (post-cursor) coefficient.
Defined at line 947 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_post_cursor_coefficient1 (typename SelfType::ValueType val)Equalization tap C+1 (post-cursor) coefficient.
Defined at line 947 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType post_cursor_coefficient2 ()Equalization tap C+2 (post-cursor) coefficient.
Defined at line 950 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_post_cursor_coefficient2 (typename SelfType::ValueType val)Equalization tap C+2 (post-cursor) coefficient.
Defined at line 950 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType cursor_coefficient ()Equalization tap C (cursor) coefficient.
Defined at line 953 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_cursor_coefficient (typename SelfType::ValueType val)Equalization tap C (cursor) coefficient.
Defined at line 953 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
hwreg::RegisterAddr<PortTransmitterEqualization> GetForDdiLane (intel_display::DdiId ddi_id, PortLane lane)Defined at line 955 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h