class TranscoderVariableRateRefreshControl

Defined at line 938 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

TRANS_VRR_CTL (VRR Control Register Transcoder)

This register is not documented for Kaby Lake or Skylake. These display

engines do not support the VRR (Variable Refresh Rate) feature.

Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 pages 1406-1407

Public Members

 field_enabled_942

 field_vblank_max_shift_ignored_952

 field_flip_line_enabled_961

 field_RsvdZ_963

 field_pipeline_full_line_count_delay_from_frame_start_973

 field_RsvdZ_975

 field_use_pipeline_full_line_count_delay_984

Public Methods

template <, >

typename SelfType::ValueType enabled ()

If true, VRR (Variable Rate Refresh) is enabled.

Defined at line 942 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

SelfType & set_enabled (typename SelfType::ValueType val)

If true, VRR (Variable Rate Refresh) is enabled.

Defined at line 942 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

SelfType & set_vblank_max_shift_ignored (typename SelfType::ValueType val)

If true, hardware varies Vblank.

If this field is true, Vblank (the Vertical Blank period) varies between

the minimum set in the TRANS_VRR_VMIN register and the maximum set in the

TRANS_VRR_VMAX register.

If this field is false, the Vblank (Vertical Blank period) in the

TRANS_VBLANK register is used.

Defined at line 952 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

typename SelfType::ValueType vblank_max_shift_ignored ()

If true, hardware varies Vblank.

If this field is true, Vblank (the Vertical Blank period) varies between

the minimum set in the TRANS_VRR_VMIN register and the maximum set in the

TRANS_VRR_VMAX register.

If this field is false, the Vblank (Vertical Blank period) in the

TRANS_VBLANK register is used.

Defined at line 952 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

typename SelfType::ValueType flip_line_enabled ()

If true, the Flip Line feature is enabled.

Changes to this field take effect at the next vertical blank.

This field must be set to true before `enabled` is true. If this field is

true, `vblank_max_shift_ignored` and `use_pipeline_full_line_count_delay`

must also be true.

Defined at line 961 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

SelfType & set_flip_line_enabled (typename SelfType::ValueType val)

If true, the Flip Line feature is enabled.

Changes to this field take effect at the next vertical blank.

This field must be set to true before `enabled` is true. If this field is

true, `vblank_max_shift_ignored` and `use_pipeline_full_line_count_delay`

must also be true.

Defined at line 961 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

typename SelfType::ValueType pipeline_full_line_count_delay_from_frame_start ()

Delay from frame start to Pipeline Full Line Count signal generation.

When `use_pipeline_full_line_count_delay` is true, this field indicates the

delay (in number of scanlines) from the start of Vblank (Vertical Blank)

start until the Pipeline Full Line Count signal is triggered. This signal

causes the start of Vactive (Vertical Active).

This field must be set to VRR Vmin - Vblank start - 4.

Defined at line 973 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

SelfType & set_pipeline_full_line_count_delay_from_frame_start (typename SelfType::ValueType val)

Delay from frame start to Pipeline Full Line Count signal generation.

When `use_pipeline_full_line_count_delay` is true, this field indicates the

delay (in number of scanlines) from the start of Vblank (Vertical Blank)

start until the Pipeline Full Line Count signal is triggered. This signal

causes the start of Vactive (Vertical Active).

This field must be set to VRR Vmin - Vblank start - 4.

Defined at line 973 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

SelfType & set_use_pipeline_full_line_count_delay (typename SelfType::ValueType val)

If true, Vertical Active starts at a programmed delay from frame start.

If this field is false, Vactive (Vertical Active) starts when a

hardware-generated Pipeline Full Line Count signal is triggered.

If this field is true, `use_pipeline_full_line_count_delay` must be

programmed correctly.

Defined at line 984 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h

template <, >

typename SelfType::ValueType use_pipeline_full_line_count_delay ()