struct
Defined at line 973 of file ../../src/graphics/display/drivers/intel-display/registers-transcoder.h
Delay from frame start to Pipeline Full Line Count signal generation.
When `use_pipeline_full_line_count_delay` is true, this field indicates the
delay (in number of scanlines) from the start of Vblank (Vertical Blank)
start until the Pipeline Full Line Count signal is triggered. This signal
causes the start of Vactive (Vertical Active).
This field must be set to VRR Vmin - Vblank start - 4.
Public Members
Field field