class DisplayPllDcoDividersTigerLake

Defined at line 855 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DPLL_CFGCR1 (Display PLL Configuration and Control Register 1?)

This register configures the frequency dividers between the DCO

(Digitally-Controlled Oscillator) in the DPLL and the DPLL's AFE (Analog

Front-End) clock output, which goes to connected DDIs. The frequency output

by the DPLL to DDIs, also called AFE clock frequency, is the DCO frequency

configured in DPLL_CFGCR1 divided by the product of all the dividers (P * Q *

K, also documented as P0 * P1 * P2) in this register.

Unfortunately, Intel's documentation refers to the DCO frequency dividers

both as (P0, P1, P2) and as (P, Q, K). Fortunately, both variations use short

names, so we can use both variations in our names below. This facilitates

checking our code against documents that use either naming variation.

This register's reserved fields are all MBZ (must be zero). So, this register

can be safely written without reading it first.

The Kaby Lake and Skylake equivalent of this register is

`DisplayPllDcoDividersTigerLake` (DPLL_CFGCR2).

Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 1 pages 651-652

DG1: IHD-OS-DG1-Vol 2c-2.21 Part 1 pages 615-616

Ice Lake: IHD-OS-ICLLP-Vol 2c-1.22-Rev2.0 Part 1 pages 473-474

Public Members

 field_RsvdZ_858

 field_q_p1_divider_select_862

 field_q_p1_divider_select_enabled_866

 field_k_p2_divider_select_899

 field_p_p0_divider_select_949

 field_reference_clock_select_1006

Public Methods

template <, >

typename SelfType::ValueType q_p1_divider_select ()

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 862 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_q_p1_divider_select (typename SelfType::ValueType val)

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 862 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

typename SelfType::ValueType q_p1_divider_select_enabled ()

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 866 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_q_p1_divider_select_enabled (typename SelfType::ValueType val)

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 866 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

uint8_t q_p1_divider ()

The value of the Q (P1) divider.

This field must not be zero. Any other value (1-255) is acceptable.

The Q divider must be 1 (disabled) if the K divider is not 2. This

requirement is also stated as ensuring a 50% duty cycle for this divider.

Defined at line 874 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DisplayPllDcoDividersTigerLake & set_q_p1_divider (uint8_t q_p1_divider)

See `q_p1_divider()` for details.

Defined at line 885 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

KP2DividerSelect k_p2_divider_select ()

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 899 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_k_p2_divider_select (KP2DividerSelect val)

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 899 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

uint8_t k_p2_divider ()

The K (P2) divider.

The preferred value is 2. If the K divider is not 2, this constrains both

the Q (P1) divider and the P (P0) divider.

This helper returns 0 if the field is set to an undocumented value.

Defined at line 907 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DisplayPllDcoDividersTigerLake & set_k_p2_divider (uint8_t k_p2_divider)

See `k_p2_divider()` for details.

Defined at line 920 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

PP0DividerSelect p_p0_divider_select ()

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 949 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_p_p0_divider_select (PP0DividerSelect val)

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 949 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

uint8_t p_p0_divider ()

The P (P0) divider.

The P (P0) divider can only be 1 if the Q (P1) divider is also 1.

This helper returns 0 if the field is set to an undocumented value.

Defined at line 956 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DisplayPllDcoDividersTigerLake & set_p_p0_divider (uint8_t p_p0_divider)

See `p_p0_divider()` for details.

Defined at line 971 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

ReferenceClockSelect reference_clock_select ()

The reference clock source for the DCO.

In most cases, this should be set to `kDisplayReference`, the XTAL (crystal

oscillator) that serves as the display engine reference frequency. The

display controller sets this for genlocked transcoders.

Defined at line 1006 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_reference_clock_select (ReferenceClockSelect val)

The reference clock source for the DCO.

In most cases, this should be set to `kDisplayReference`, the XTAL (crystal

oscillator) that serves as the display engine reference frequency. The

display controller sets this for genlocked transcoders.

Defined at line 1006 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

hwreg::RegisterAddr<DisplayPllDcoDividersTigerLake> GetForDpll (intel_display::PllId pll_id)

Defined at line 1008 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

Enumerations

enum KP2DividerSelect

Name	Value
k1	0b001
k2	0b010
k3	0b100

Possible values for the `k_p2_divider_select` field.

Defined at line 891 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

enum PP0DividerSelect

Name	Value
k2	0b0001
k3	0b0010
k5	0b0100
k7	0b1000

Documented values for the `p_p0_divider_select` field.

Defined at line 940 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

enum ReferenceClockSelect

Name	Value
kDisplayReference	0b00
kUnfilteredGenlock	0b01
kInvalid	0b10
kFilteredGenlock	0b11

Possible values for the `reference_clock_select` field.

Defined at line 994 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h