class MemoryAddressDecoderDimmParametersAlderLake

Defined at line 504 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

MAD_DIMM_CH0_0_0_0_MCHBAR (Channel 0 DIMM Characteristics)

MAD_DIMM_CH1_0_0_0_MCHBAR (Channel 1 DIMM Characteristics)

Raptor Lake: 743846-001 Sections 3.2.49-3.2.50 pages 128-130

Alder Lake S: 655259-003 Sections 3.2.45-3.2.46 pages 110-112

Alder Lake H: 710723-003 Sections 3.2.45-3.2.46 pages 136-137

Public Members

 field_enable_extended_bank_hashing_b_515

 field_enable_extended_bank_hashing_a_518

 field_bank_group_bit_options_525

 field_dimm_s_rank_count_minus_1_530

 field_dimm_s_ddr_chip_width_select_533

 field_RsvdZ_535

 field_dimm_s_size_512mb_538

 field_RsvdZ_540

 field_ddr5_dimm_l_capacity_is_8gb_545

 field_ddr5_dimm_s_capacity_is_8gb_550

 field_dimm_l_rank_count_minus_1_555

 field_dimm_l_ddr_chip_width_select_557

 field_dimm_l_size_512mb_560

Public Methods

template <, >

typename SelfType::ValueType enable_extended_bank_hashing_b ()

If true, XaB (extended bank hashing B) is enabled in the address decoder.

Defined at line 515 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_enable_extended_bank_hashing_b (typename SelfType::ValueType val)

If true, XaB (extended bank hashing B) is enabled in the address decoder.

Defined at line 515 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType enable_extended_bank_hashing_a ()

If true, XbB (extended bank hashing A) is enabled in the address decoder.

Defined at line 518 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_enable_extended_bank_hashing_a (typename SelfType::ValueType val)

If true, XbB (extended bank hashing A) is enabled in the address decoder.

Defined at line 518 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType bank_group_bit_options ()

Selects how zone address bits feed into BG and CAS bits.

This field's value influences the computation of BG0/1 (Bank Group bits 0

and 1) and CAS5/6 (column address bits 5 and 6). The address computation

depends on the DDR type and the value in this field.

Defined at line 525 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_bank_group_bit_options (typename SelfType::ValueType val)

Selects how zone address bits feed into BG and CAS bits.

This field's value influences the computation of BG0/1 (Bank Group bits 0

and 1) and CAS5/6 (column address bits 5 and 6). The address computation

depends on the DDR type and the value in this field.

Defined at line 525 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_s_rank_count_minus_1 ()

The number of ranks in DIMM S. 0 = 1 rank, ... 3 = 4 ranks.

Values above 1 (2 ranks) are not valid for for DIMM S.

Defined at line 530 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_s_rank_count_minus_1 (typename SelfType::ValueType val)

The number of ranks in DIMM S. 0 = 1 rank, ... 3 = 4 ranks.

Values above 1 (2 ranks) are not valid for for DIMM S.

Defined at line 530 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

DdrChipWidthValue dimm_s_ddr_chip_width_select ()

The DDR chip width for DIMM S.

Defined at line 533 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_s_ddr_chip_width_select (DdrChipWidthValue val)

The DDR chip width for DIMM S.

Defined at line 533 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_s_size_512mb ()

Size of DIMM S in multiples of 0.5 GB (512 MB).

Defined at line 538 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_s_size_512mb (typename SelfType::ValueType val)

Size of DIMM S in multiples of 0.5 GB (512 MB).

Defined at line 538 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType ddr5_dimm_l_capacity_is_8gb ()

If false, DIMM L capacity exceeds 8GB.

This bit must be false for non-DDR5 configurations.

Defined at line 545 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_ddr5_dimm_l_capacity_is_8gb (typename SelfType::ValueType val)

If false, DIMM L capacity exceeds 8GB.

This bit must be false for non-DDR5 configurations.

Defined at line 545 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType ddr5_dimm_s_capacity_is_8gb ()

If false, DIMM S capacity exceeds 8GB.

This bit must be false for non-DDR5 configurations.

Defined at line 550 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_ddr5_dimm_s_capacity_is_8gb (typename SelfType::ValueType val)

If false, DIMM S capacity exceeds 8GB.

This bit must be false for non-DDR5 configurations.

Defined at line 550 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_l_rank_count_minus_1 ()

The number of ranks in DIMM L. 0 = 1 rank, 1 = 2 ranks ... 3 = 4 ranks.

Values above 1 (2 ranks) are only valid in ERM (Enhanced Rank Mode).

Defined at line 555 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_l_rank_count_minus_1 (typename SelfType::ValueType val)

The number of ranks in DIMM L. 0 = 1 rank, 1 = 2 ranks ... 3 = 4 ranks.

Values above 1 (2 ranks) are only valid in ERM (Enhanced Rank Mode).

Defined at line 555 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

DdrChipWidthValue dimm_l_ddr_chip_width_select ()

Defined at line 557 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_l_ddr_chip_width_select (DdrChipWidthValue val)

Defined at line 557 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_l_size_512mb ()

Size of DIMM L in multiples of 0.5 GB (512 MB).

Defined at line 560 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_l_size_512mb (typename SelfType::ValueType val)

Size of DIMM L in multiples of 0.5 GB (512 MB).

Defined at line 560 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_s_ddr_chip_width ()

The width of the DDR chips in DIMM S.

Defined at line 563 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_l_ddr_chip_width ()

The width of the DDR chips in DIMM L.

Defined at line 568 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_s_rank_count ()

The number of ranks in DIMM S.

Defined at line 573 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_l_rank_count ()

The number of ranks in DIMM L.

Defined at line 580 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_s_size_mb ()

The size of DIMM S, in MB.

Defined at line 587 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_l_size_mb ()

The size of DIMM L, in MB.

Defined at line 594 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

hwreg::RegisterAddr<MemoryAddressDecoderDimmParametersAlderLake> GetForControllerAndChannel (int memory_controller_index, int channel_index)

Defined at line 600 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

Enumerations

enum DdrChipWidthValue

Name	Value
kX8	0b00
kX16	0b01
kX32	0b10
kReserved	0b11

Defined at line 507 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h