class ArbitrationControl2
Defined at line 154 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ARB_CTL (Display Arbitration Control 2)
This register has bits that are reserved but not MBZ (must be zero). So, it
can only be safely updated via read-modify-write operations.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 1 pages 54-56
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 1 pages 13-15
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 82-83
Skylake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 81-82
Public Members
field_RsvdZ_156
field_display_capture_write_request_limit_bits_163
field_display_state_buffer_write_request_limit_tiger_lake_bits_170
field_RsvdZ_172
field_par5_request_limit_tiger_lake_bits_181
field_framebuffer_compression_request_limit_tiger_lake_bits_188
field_RsvdZ_190
field_high_priority_requests_enable_trickle_feed_requests_202
field_max_inflight_low_priority_read_requests_bits_209
field_RsvdZ_211
field_max_inflight_high_priority_read_requests_bits_218
field_isochronous_priority_control_enabled_231
field_RsvdZ_233
field_request_transaction_id_queue_watermark_bits_240
Public Methods
template <, >
typename SelfType::ValueType display_capture_write_request_limit_bits ()
Maximum number of write requests accepted from WD (display capture).
This field has a non-trivial encoding. It should be used via the helpers
`display_capture_write_request_limit()` and
`set_display_capture_write_request_limit()`.
Defined at line 163 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_display_capture_write_request_limit_bits (typename SelfType::ValueType val)
Maximum number of write requests accepted from WD (display capture).
This field has a non-trivial encoding. It should be used via the helpers
`display_capture_write_request_limit()` and
`set_display_capture_write_request_limit()`.
Defined at line 163 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType display_state_buffer_write_request_limit_tiger_lake_bits ()
Maximum number of write requests accepted from DSB (Display State Buffer).
This field has a non-trivial encoding. It should be used via the helpers
`display_state_buffer_write_request_limit_tiger_lake()` and
`set_display_state_buffer_write_request_limit_tiger_lake()`.
Defined at line 170 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_display_state_buffer_write_request_limit_tiger_lake_bits (typename SelfType::ValueType val)
Maximum number of write requests accepted from DSB (Display State Buffer).
This field has a non-trivial encoding. It should be used via the helpers
`display_state_buffer_write_request_limit_tiger_lake()` and
`set_display_state_buffer_write_request_limit_tiger_lake()`.
Defined at line 170 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType par5_request_limit_tiger_lake_bits ()
Maximum number of requests accepted from "par5".
"par5" does not appear to be documented.
This field does not exist on Kaby Lake or Skylake.
This field has a non-trivial encoding.
Defined at line 181 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_par5_request_limit_tiger_lake_bits (typename SelfType::ValueType val)
Maximum number of requests accepted from "par5".
"par5" does not appear to be documented.
This field does not exist on Kaby Lake or Skylake.
This field has a non-trivial encoding.
Defined at line 181 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType framebuffer_compression_request_limit_tiger_lake_bits ()
Maximum number of requests accepted from FBC (framebuffer compression).
This field has a non-trivial encoding. It should be used via the helpers
`framebuffer_compression_request_limit_tiger_lake()` and
`set_framebuffer_compression_request_limit_tiger_lake()`.
Defined at line 188 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_framebuffer_compression_request_limit_tiger_lake_bits (typename SelfType::ValueType val)
Maximum number of requests accepted from FBC (framebuffer compression).
This field has a non-trivial encoding. It should be used via the helpers
`framebuffer_compression_request_limit_tiger_lake()` and
`set_framebuffer_compression_request_limit_tiger_lake()`.
Defined at line 188 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType high_priority_requests_enable_trickle_feed_requests ()
If true, a HP request causes the arbiter to accept trickle feed requests.
Trickle feed requests are sent by DBUF (Display Buffer) clients that
react immediately when a DBUF block that they own frees up. By contrast,
DBUF clients may send batched requests after a few blocks free up. The
concept was most recently documented in IHD-OS-VLV-Vol10-04.14 (the
Valleyview Display Engine PRM).
If this bit is enabled, the arbiter allows trickle feed requests from all
clients when it receives a HP (high-priority) request from one client.
Defined at line 202 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_high_priority_requests_enable_trickle_feed_requests (typename SelfType::ValueType val)
If true, a HP request causes the arbiter to accept trickle feed requests.
Trickle feed requests are sent by DBUF (Display Buffer) clients that
react immediately when a DBUF block that they own frees up. By contrast,
DBUF clients may send batched requests after a few blocks free up. The
concept was most recently documented in IHD-OS-VLV-Vol10-04.14 (the
Valleyview Display Engine PRM).
If this bit is enabled, the arbiter allows trickle feed requests from all
clients when it receives a HP (high-priority) request from one client.
Defined at line 202 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType max_inflight_low_priority_read_requests_bits ()
The maximum number of in-flight LP (low-priority) read transactions.
This field has a non-trivial encoding. It should be used via the helpers
`max_inflight_low_priority_read_requests()` and
`set_max_inflight_low_priority_read_requests()`.
Defined at line 209 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_max_inflight_low_priority_read_requests_bits (typename SelfType::ValueType val)
The maximum number of in-flight LP (low-priority) read transactions.
This field has a non-trivial encoding. It should be used via the helpers
`max_inflight_low_priority_read_requests()` and
`set_max_inflight_low_priority_read_requests()`.
Defined at line 209 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType max_inflight_high_priority_read_requests_bits ()
The maximum number of in-flight HP (high-priority) read transactions.
This field has a non-trivial encoding. It should be used via the helpers
`max_inflight_high_priority_read_requests()` and
`set_max_inflight_high_priority_read_requests()`.
Defined at line 218 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_max_inflight_high_priority_read_requests_bits (typename SelfType::ValueType val)
The maximum number of in-flight HP (high-priority) read transactions.
This field has a non-trivial encoding. It should be used via the helpers
`max_inflight_high_priority_read_requests()` and
`set_max_inflight_high_priority_read_requests()`.
Defined at line 218 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType isochronous_priority_control_enabled ()
If false, the Display Engine always sends requests at isochronous priority.
If true, the Display Engine may issue request at lower priority, which may
improve performance for other memory-bound workloads. The Display Engine's
requests will be demoted once the relevant transition watermark is reached.
If the transition watermark is not enabled, the Display Engine's requests
are demoted once the DBUF (Display Buffer) is full.
The hardware only reads this bit from the global arbiter's configuration.
Other arbiters, such as Arbiter 1 and 2 on Tiger Lake, use the global
arbiter's setting.
Defined at line 231 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_isochronous_priority_control_enabled (typename SelfType::ValueType val)
If false, the Display Engine always sends requests at isochronous priority.
If true, the Display Engine may issue request at lower priority, which may
improve performance for other memory-bound workloads. The Display Engine's
requests will be demoted once the relevant transition watermark is reached.
If the transition watermark is not enabled, the Display Engine's requests
are demoted once the DBUF (Display Buffer) is full.
The hardware only reads this bit from the global arbiter's configuration.
Other arbiters, such as Arbiter 1 and 2 on Tiger Lake, use the global
arbiter's setting.
Defined at line 231 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
typename SelfType::ValueType request_transaction_id_queue_watermark_bits ()
Minimum RTID queue size required to start HP (high-priority) transactions.
This field has a non-trivial encoding. It should be used via the helpers
`request_transaction_id_queue_watermark()` and
`set_request_transaction_id_queue_watermark()`.
Defined at line 240 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >
SelfType & set_request_transaction_id_queue_watermark_bits (typename SelfType::ValueType val)
Minimum RTID queue size required to start HP (high-priority) transactions.
This field has a non-trivial encoding. It should be used via the helpers
`request_transaction_id_queue_watermark()` and
`set_request_transaction_id_queue_watermark()`.
Defined at line 240 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t display_capture_write_request_limit ()
Maximum number of write requests accepted from WD (display capture).
WD (Wireless Display / display capture) transcoders issue LP (low-priority)
write requests. Re-arbitration occurs after this limit is hit.
Defined at line 246 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl2 & set_display_capture_write_request_limit (int32_t request_limit)
See `display_capture_write_request_limit()` for details.
Defined at line 253 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t display_state_buffer_write_request_limit_tiger_lake ()
Maximum number of write requests accepted from DSB (Display State Buffer).
DSB (Display State Buffer) engines issues LP (low-priority) write requests.
Re-arbitration occurs after this limit is hit.
This field does not exist on Kaby Lake or Skylake.
Defined at line 264 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl2 & set_display_state_buffer_write_request_limit_tiger_lake (int32_t request_limit)
See `display_state_buffer_write_request_limit_tiger_lake()` for details.
Defined at line 271 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t par5_request_limit_tiger_lake ()
Maximum number of requests accepted from "par5".
The "par5" client / feature does not appear to be documented. Nevertheless,
re-arbitration occurs after this limit is hit.
This field does not exist on Kaby Lake or Skylake.
Defined at line 283 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl2 & set_par5_request_limit_tiger_lake (int32_t request_limit)
See `par5_request_limit_tiger_lake()` for details.
Defined at line 291 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t framebuffer_compression_request_limit_tiger_lake ()
Maximum number of requests accepted from FBC (framebuffer compression).
The FBC (framebuffer compression) feature issues LP (low-priority) write
requests to update the compressed framebuffer. Re-arbitration occurs after
this limit is hit.
This field does not exist on Kaby Lake or Skylake.
Defined at line 306 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl2 & set_framebuffer_compression_request_limit_tiger_lake (int32_t request_limit)
See `framebuffer_compression_request_limit_tiger_lake()` for details.
Defined at line 313 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t max_inflight_low_priority_read_requests ()
The maximum number of in-flight LP (low-priority) read transactions.
Defined at line 319 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl2 & set_max_inflight_low_priority_read_requests (int32_t max_requests)
See `max_inflight_low_priority_read_requests()` for details.
Defined at line 326 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t max_inflight_high_priority_read_requests ()
The maximum number of in-flight HP (high-priority) read transactions.
Defined at line 335 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl2 & set_max_inflight_high_priority_read_requests (int32_t max_requests)
See `max_inflight_high_priority_read_requests()` for details.
Defined at line 342 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t request_transaction_id_queue_watermark ()
Minimum RTID queue size required to start HP (high-priority) transactions.
RTIDs (Request Transaction IDs) are credits issued by the per-processor
cache coherence coordinator, which is the CHA (combined Caching and Home
Agent) on recent CPU models. These credits track outstanding transactions
across the cache coherence bus, which is UPI (Ultra-Path Interconnect) on
recent CPU models, and QPI (Quick-Path Interconnect) on older models. The
"RTID" acronym is defined in some processor datasheets, such as document
735086 (Ice Lake Xeon processor datasheet, volume 2). The CHA is described
at a very high level in uncore performance monitoring manuals, such as
document
This watermark is the minimum level of the RTID FIFO (queue) required for
the arbiter to start HP (high-priority) transactions.
The pseudocode in IHD-OS-TGL-Vol 12-1.22-Rev2.0 "Bandwidth Restrictions" >
"Available Memory Bandwidth Calculation" on pages 163-166 suggests that
each memory transaction (on each DRAM channel) requires an RTID.
Defined at line 369 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl2 & set_request_transaction_id_queue_watermark (int32_t watermark)
See `request_transaction_id_queue_watermark()` for details.
Defined at line 376 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
hwreg::RegisterAddr<ArbitrationControl2> GetForArbiter (int arbiter_index)
`arbiter_index` zero (0) represents the global arbiter. The following
indexes represent the numbered arbiters.
Kaby Lake and Skylake only have a global arbiter.
Defined at line 388 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h