class PortPhysicalCoding1
Defined at line 639 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
PORT_PCS_DW1 (Physical Coding Sublayer config double-word 1?)
This register has bits that are reserved but not MBZ (must be zero). So, it
can only be safely updated via read-modify-write operations.
This register is not documented on Kaby Lake or Skylake.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 pages 903-907
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 2 pages 917-921
Ice Lake: IHD-OS-ICLLP-Vol 2c-1.22-Rev2.0 Part 2 pages 573-575
Public Members
field_RsvdZ_649 field_common_mode_keeper_enabled_while_power_gated_651 field_power_gate_powered_down_654 field_common_mode_keeper_enabled_660 field_common_mode_keeper_bias_control_661 field_RsvdZ_663 field_duty_cycle_correction_schedule_select_666 field_duty_cycle_correction_calibration_bypassed_673 field_duty_cycle_correction_calibration_on_wake_679 field_force_transmitter_duty_cycle_correction_calibration_685 field_RsvdZ_687 field_transmitter_high_689 field_RsvdZ_691 field_clock_request_693 field_use_transmitter_buffer_clock_as_symbol_clock_696 field_transmitter_fifo_reset_main_override_valid_699 field_transmitter_fifo_reset_main_override_704 field_transmitter_deemphasis_value_706 field_latency_optimization_value_708 field_soft_lane_reset_valid_711 field_soft_lane_reset_716Public Methods
template <, >typename SelfType::ValueType common_mode_keeper_enabled_while_power_gated ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 651 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_common_mode_keeper_enabled_while_power_gated (typename SelfType::ValueType val)Defined at line 651 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType power_gate_powered_down ()If true, the pins are power-gated (powered off).
Defined at line 654 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_power_gate_powered_down (typename SelfType::ValueType val)If true, the pins are power-gated (powered off).
Defined at line 654 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType common_mode_keeper_enabled ()Enables the common mode voltage keeper circuit.
The common keeper preserves the common-mode voltage between the pair of
pins during low power modes.
Defined at line 660 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_common_mode_keeper_enabled (typename SelfType::ValueType val)Enables the common mode voltage keeper circuit.
The common keeper preserves the common-mode voltage between the pair of
pins during low power modes.
Defined at line 660 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType common_mode_keeper_bias_control ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 661 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_common_mode_keeper_bias_control (typename SelfType::ValueType val)Defined at line 661 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >DutyCycleCorrectionScheduleSelect duty_cycle_correction_schedule_select ()Selects how often DCC (Duty Cycle Correction) is performed.
Defined at line 666 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_duty_cycle_correction_schedule_select (DutyCycleCorrectionScheduleSelect val)Selects how often DCC (Duty Cycle Correction) is performed.
Defined at line 666 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType duty_cycle_correction_calibration_bypassed ()If true, the DCC (Duty Cycle Correction) calibration is bypassed.
Setting this to true also bypasses DFx (design for debug/test) receiver
calibration. The two bypasses share a signal in the PCS (Physical Coding
Sublayer).
Defined at line 673 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_duty_cycle_correction_calibration_bypassed (typename SelfType::ValueType val)If true, the DCC (Duty Cycle Correction) calibration is bypassed.
Setting this to true also bypasses DFx (design for debug/test) receiver
calibration. The two bypasses share a signal in the PCS (Physical Coding
Sublayer).
Defined at line 673 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType duty_cycle_correction_calibration_on_wake ()If true, DCC calibration will be performed on the next power up.
Setting this to true forces a DCC (Duty Cycle Correction) calibration the
next time the DL (downlink) is woken up after a power down event.
Defined at line 679 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_duty_cycle_correction_calibration_on_wake (typename SelfType::ValueType val)If true, DCC calibration will be performed on the next power up.
Setting this to true forces a DCC (Duty Cycle Correction) calibration the
next time the DL (downlink) is woken up after a power down event.
Defined at line 679 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType force_transmitter_duty_cycle_correction_calibration ()If true, forces a transmitter DCC (Duty Cycle Correction) calibration.
This field should only be used (set to true) after the boot-time
initialization completes.
Defined at line 685 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_force_transmitter_duty_cycle_correction_calibration (typename SelfType::ValueType val)If true, forces a transmitter DCC (Duty Cycle Correction) calibration.
This field should only be used (set to true) after the boot-time
initialization completes.
Defined at line 685 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_transmitter_high (typename SelfType::ValueType val)Defined at line 689 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType transmitter_high ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 689 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType clock_request ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 693 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_clock_request (typename SelfType::ValueType val)Defined at line 693 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_use_transmitter_buffer_clock_as_symbol_clock (typename SelfType::ValueType val)If true, the lane's symbol clock is the TBC (Transmitter Buffer Clock).
Defined at line 696 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType use_transmitter_buffer_clock_as_symbol_clock ()If true, the lane's symbol clock is the TBC (Transmitter Buffer Clock).
Defined at line 696 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_transmitter_fifo_reset_main_override_valid (typename SelfType::ValueType val)If false, `transmitter_fifo_reset_main_override` is ignored.
Defined at line 699 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType transmitter_fifo_reset_main_override_valid ()If false, `transmitter_fifo_reset_main_override` is ignored.
Defined at line 699 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_transmitter_fifo_reset_main_override (typename SelfType::ValueType val)Reset Main override for the transmitter's FIFO.
Ignored if `transmitter_fifo_reset_main_override_valid` is false
Defined at line 704 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType transmitter_fifo_reset_main_override ()Reset Main override for the transmitter's FIFO.
Ignored if `transmitter_fifo_reset_main_override_valid` is false
Defined at line 704 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_transmitter_deemphasis_value (typename SelfType::ValueType val)Defined at line 706 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType transmitter_deemphasis_value ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 706 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType latency_optimization_value ()NOLINTEND(misc-non-private-member-variables-in-classes)
Defined at line 708 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_latency_optimization_value (typename SelfType::ValueType val)Defined at line 708 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_soft_lane_reset_valid (typename SelfType::ValueType val)If true, `soft_lane_reset` is read by the circuitry.
Defined at line 711 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType soft_lane_reset_valid ()If true, `soft_lane_reset` is read by the circuitry.
Defined at line 711 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >SelfType & set_soft_lane_reset (typename SelfType::ValueType val)If false, requests that the lanes controlled by this register are reset.
This field is only used if `soft_lane_reset_valid` is true.
Defined at line 716 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
template <, >typename SelfType::ValueType soft_lane_reset ()If false, requests that the lanes controlled by this register are reset.
This field is only used if `soft_lane_reset_valid` is true.
Defined at line 716 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
hwreg::RegisterAddr<PortPhysicalCoding1> GetForDdiLane (intel_display::DdiId ddi_id, PortLane lane)Defined at line 718 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
uint32_t MmioAddressForDdiLane (intel_display::DdiId ddi_id, PortLane lane)Returns the base address of lane's PORT_PCS_ configuration registers.
Defined at line 723 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h
Enumerations
enum DutyCycleCorrectionScheduleSelect| Name | Value |
|---|---|
| kOnce | 0b00 |
| kEvery100Microseconds | 0b01 |
| kEvery1000Microseconds | 0b10 |
| kContinuously | 0b11 |
Possible values for the `duty_cycle_correction_schedule_select` field.
Defined at line 642 of file ../../src/graphics/display/drivers/intel-display/registers-ddi-phy-tiger-lake.h