class PchPanelPowerOnDelays

Defined at line 347 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

PP_ON_DELAYS (Panel Power On Sequencing Delays)

Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 page 964

DG1: IHD-OS-DG1-Vol 2c-2.21 Part 2 page 989

Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 2 page 630

Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 2 page 624

Public Members

 field_RsvdZ_349

 field_power_on_to_hpd_aux_ready_delay_353

 field_RsvdZ_355

 field_power_on_to_backlight_on_delay_364

template <, >

typename SelfType::ValueType power_on_to_hpd_aux_ready_delay ()

eDP T3 - Expected delay from enabling panel power to HPD and AUX ready.

eDP T3 = register value * 100us.

Defined at line 353 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_power_on_to_hpd_aux_ready_delay (typename SelfType::ValueType val)

eDP T3 - Expected delay from enabling panel power to HPD and AUX ready.

eDP T3 = register value * 100us.

Defined at line 353 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

typename SelfType::ValueType power_on_to_backlight_on_delay ()

Minimum delay from power on until the backlight can be enabled.

The PCH will not enable the backlight until T3 and this delay have passed.

Delay = register value * 100us.

This seems to match eDP T2 - the minimum delay from enabling panel

power to Automatic Black Video Generation, where the panel renders black

video instead of noise when it gets an invalid video signal.

Defined at line 364 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_power_on_to_backlight_on_delay (typename SelfType::ValueType val)