class PipeArbiterControl
Defined at line 759 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
PIPE_ARB_CTL (Pipe Arbiter Control)
This register does not exist on Kaby Lake or Skylake.
This register has bits that are reserved but not MBZ (must be zero). So, it
can only be safely updated via read-modify-write operations.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 2 pages 669-670
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 2 pages 669-670
Public Members
field_RsvdZ_761 field_weighted_arbitration_disabled_764 field_arbitration_cycle_additional_slots_769 field_RsvdZ_771 field_plane_control_slot_config_enabled_778 field_block_validity_check_disabled_781 field_display_stream_buffer_arbitration_interval_bits_786 field_display_buffer_requests_per_streamer_request_bits_793 field_RsvdZ_795 field_display_buffer_drain_delay_after_frame_start_us_798Public Methods
template <, >SelfType & set_weighted_arbitration_disabled (typename SelfType::ValueType val)If true, weighted pipe slice arbitration is disabled.
Defined at line 764 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType weighted_arbitration_disabled ()If true, weighted pipe slice arbitration is disabled.
Defined at line 764 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType arbitration_cycle_additional_slots ()Number of additional slots added to an arbitration cycle.
During these additional slots, clients are served using round-robin.
Defined at line 769 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_arbitration_cycle_additional_slots (typename SelfType::ValueType val)Number of additional slots added to an arbitration cycle.
During these additional slots, clients are served using round-robin.
Defined at line 769 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType plane_control_slot_config_enabled ()If true, arbitration configuration in `PlaneControl` (PLANE_CTL) is used.
This field enables the use of the
`pipe_slice_request_arbitration_slot_count_tiger_lake` field.
If this field is false, hardware defaults are used instead.
Defined at line 778 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_plane_control_slot_config_enabled (typename SelfType::ValueType val)If true, arbitration configuration in `PlaneControl` (PLANE_CTL) is used.
This field enables the use of the
`pipe_slice_request_arbitration_slot_count_tiger_lake` field.
If this field is false, hardware defaults are used instead.
Defined at line 778 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType block_validity_check_disabled ()If true, the pipe arbiter does not check for block validity.
Defined at line 781 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_block_validity_check_disabled (typename SelfType::ValueType val)If true, the pipe arbiter does not check for block validity.
Defined at line 781 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType display_stream_buffer_arbitration_interval_bits ()The DSB (Display Stream Buffer) engine service interval, in clock cycles.
This field has a non-trivial encoding.
Defined at line 786 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_display_stream_buffer_arbitration_interval_bits (typename SelfType::ValueType val)The DSB (Display Stream Buffer) engine service interval, in clock cycles.
This field has a non-trivial encoding.
Defined at line 786 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType display_buffer_requests_per_streamer_request_bits ()Number of DBUF (Display Buffer) requests serviced per streamer request.
This field has a non-trivial encoding. It should be used via the
`display_buffer_requests_per_streamer_request()` and
`set_display_buffer_requests_per_streamer_request()` helpers.
Defined at line 793 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_display_buffer_requests_per_streamer_request_bits (typename SelfType::ValueType val)Number of DBUF (Display Buffer) requests serviced per streamer request.
This field has a non-trivial encoding. It should be used via the
`display_buffer_requests_per_streamer_request()` and
`set_display_buffer_requests_per_streamer_request()` helpers.
Defined at line 793 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType display_buffer_drain_delay_after_frame_start_us ()Number of microseconds the pipe waits after frame start to drain DBUF data.
Defined at line 798 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_display_buffer_drain_delay_after_frame_start_us (typename SelfType::ValueType val)Number of microseconds the pipe waits after frame start to drain DBUF data.
Defined at line 798 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t display_stream_buffer_arbitration_interval ()The DSB (Display Stream Buffer) engine service interval, in clock cycles.
This field has a non-trivial encoding.
Defined at line 803 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
PipeArbiterControl & set_display_stream_buffer_arbitration_interval (int32_t clocks)See `display_stream_buffer_arbitration_interval()` for details.
Defined at line 810 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t display_buffer_requests_per_streamer_request ()Number of DBUF (Display Buffer) requests serviced per streamer request.
The register's documentation uses the DDB acronym (Display Data Buffer)
instead of DBUF. IHD-OS-TGL-Vol 12-1.22-Rev2.0 section "Maximum Data Buffer
Bandwidth" on page 167 contains "display data buffer (DBUF)", which hints
that DBUF and DDB are synonyms. The hint is confirmed by the intel-display
driver code, which uses both "ddb" and "dbuf" in DBUF-related identifiers.
The "streamer" referenced here is most likely the plane's display streamer,
which issues memory requests when the plane's free DBUF space exceeds its
watermark. This streamer is mentioned as the "display streamer" or "overlay
streamer" in older documentation, such as the "FW1 - Display FIFO Watermark
Control 1" section in IHD-OS-VLV-Vol10-04.14 (the Display PRM for
ValleyView graphics). Older documentation had specific names ("display",
"overlay" / "sprite", "cursor") for planes, used the term "display RAM"
instead of DBUF, and the term "display FIFO" to refer to a plane's DBUF
allocation. The "display FIFO" concept is briefly covered in the "DSPARB -
Display Arbitration Control" section in IHD-OS-VLV-Vol10-04.14. These terms
still appear in current documentation, and in Intel's driver code.
Defined at line 838 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
PipeArbiterControl & set_display_buffer_requests_per_streamer_request (int32_t display_buffer_requests)See `display_buffer_requests_per_streamer_request()` for details.
Defined at line 845 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
hwreg::RegisterAddr<PipeArbiterControl> GetForPipe (intel_display::PipeId pipe_id)Defined at line 856 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h