class DisplayPllDcoDividersKabyLake

Defined at line 486 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DPLL_CFGCR2 (Display PLL Configuration and Control Register 2?)

When the DPLL (Display PLL) operates in HDMI mode, this register configures

the frequency dividers between the DCO (Digitally-Controlled Oscillator) in

the DPLL and the DPLL's AFE (Analog Front-End) clock output, which goes to

connected DDIs. The frequency output by the DPLL to DDIs, also called AFE

clock frequency, is the DCO frequency configured in DPLL_CFGCR1 divided by

the product of all the dividers (P * Q * K, also documented as P0 * P1 * P2)

in this register.

Unfortunately, Intel's documentation refers to the DCO frequency dividers

both as (P0, P1, P2) and as (P, Q, K). Fortunately, both variations use short

names, so we can use both variations in our names below. This facilitates

checking our code against documents that use either naming variation.

This register's reserved fields are all MBZ (must be zero). So, this register

can be safely written without reading it first.

The Tiger Lake equivalent of this register is DPLL_CFGCR1.

Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1 page 526-527

Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 1 pages 524-525

Public Members

 field_RsvdZ_512

 field_q_p1_divider_select_516

 field_q_p1_divider_select_enabled_520

 field_k_p2_divider_select_524

 field_p_p0_divider_select_528

 field_center_frequency_select_532

Public Methods

template <, >

typename SelfType::ValueType q_p1_divider_select ()

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 516 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_q_p1_divider_select (typename SelfType::ValueType val)

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 516 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

typename SelfType::ValueType q_p1_divider_select_enabled ()

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 520 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_q_p1_divider_select_enabled (typename SelfType::ValueType val)

This field has a non-trivial representation and should be accessed via the

`q_p1_divider() and `set_q_p1_divider()` helpers.

Defined at line 520 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

KP2DividerSelect k_p2_divider_select ()

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 524 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_k_p2_divider_select (KP2DividerSelect val)

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 524 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

PP0DividerSelect p_p0_divider_select ()

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 528 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_p_p0_divider_select (PP0DividerSelect val)

This field has a non-trivial representation and should be accessed via the

`k_p2_divider() and `set_k_p2_divider()` helpers.

Defined at line 528 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

CenterFrequencySelect center_frequency_select ()

This field has a non-trivial representation and should be accessed via the

`center_frequency_mhz()` and `set_center_frequency_mhz()` helpers.

Defined at line 532 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

template <, >

SelfType & set_center_frequency_select (CenterFrequencySelect val)

This field has a non-trivial representation and should be accessed via the

`center_frequency_mhz()` and `set_center_frequency_mhz()` helpers.

Defined at line 532 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

uint8_t k_p2_divider ()

The K (P2) divider.

The preferred value is 2. If the K divider is not 2, this constrains both

the Q (P1) divider and the P (P0) divider.

Defined at line 538 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

uint8_t q_p1_divider ()

The value of the Q (P1) divider.

This field must not be zero. Any other value (1-255) is acceptable.

The Q divider must be 1 (disabled) if the K divider is not 2. This

requirement is also stated as ensuring a 50% duty cycle for this divider.

Defined at line 560 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DisplayPllDcoDividersKabyLake & set_q_p1_divider (uint8_t q_p1_divider)

See `q_p1_divider()` for details.

Defined at line 571 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DisplayPllDcoDividersKabyLake & set_k_p2_divider (uint8_t k_p2_divider)

See `k_p2_divider()` for details.

Defined at line 577 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

uint8_t p_p0_divider ()

The P (P0) divider.

The P (P0) divider can only be 1 if the Q (P1) divider is also 1.

This helper returns 0 if the field is set to an undocumented value.

Defined at line 604 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DisplayPllDcoDividersKabyLake & set_p_p0_divider (uint8_t p_p0_divider)

See `p_p0_divider()` for details.

Defined at line 619 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

int16_t center_frequency_mhz ()

The center frquency for the DPLL's DCO, in Mhz.

The DCO frequency configured in the DisplayPllDcoFrequencyKabyLake register must be

within [-6%, +1%] of the selected center frequency.

This helper returns 0 if the field is set to an undocumented value.

Defined at line 647 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

DisplayPllDcoDividersKabyLake & set_center_frequency_mhz (int16_t center_frequency_mhz)

See `center_frequency_mhz()` for details.

Defined at line 660 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

hwreg::RegisterAddr<DisplayPllDcoDividersKabyLake> GetForDpll (intel_display::PllId pll_id)

Defined at line 679 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

Enumerations

enum KP2DividerSelect

Name	Value
k5	0b00
k2	0b01
k3	0b10
k1	0b11

Possible values for the `k_p2_divider_select` field.

Defined at line 490 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

enum PP0DividerSelect

Name	Value
k1	0b000
k2	0b001
k3	0b010
k7	0b100

Documented values for the `p_p0_divider_select` field.

Defined at line 498 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

enum CenterFrequencySelect

Name	Value
k9600Mhz	0b00
k9000Mhz	0b01
k8400Mhz	0b11

Possible values for the `center_frequency_select` field.

Defined at line 506 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h

Records