class PipeInterrupt

Defined at line 735 of file ../../src/graphics/display/drivers/intel-display/registers-pipe.h

DE_PIPE_INTERRUPT (Display Engine Pipe Interrupts)

Tiger Lake: IHD-OS-TGL-Vol 2c-12.21 Part 1 pages 361-364

Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 448-450

Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 1 pages 444-446

Public Members

 field_underrun_738

 field_vsync_741

 field_vblank_753

template <, >

SelfType & set_underrun (typename SelfType::ValueType val)

The attached transcoder experienced an underrun.

Defined at line 738 of file ../../src/graphics/display/drivers/intel-display/registers-pipe.h

template <, >

typename SelfType::ValueType underrun ()

The attached transcoder experienced an underrun.

Defined at line 738 of file ../../src/graphics/display/drivers/intel-display/registers-pipe.h

template <, >

SelfType & set_vsync (typename SelfType::ValueType val)

Active high level while the attached transcoder is in vertical sync.

Defined at line 741 of file ../../src/graphics/display/drivers/intel-display/registers-pipe.h

template <, >

typename SelfType::ValueType vsync ()

Active high level while the attached transcoder is in vertical sync.

Defined at line 741 of file ../../src/graphics/display/drivers/intel-display/registers-pipe.h

template <, >

SelfType & set_vblank (typename SelfType::ValueType val)

Active high level while the attached transcoder is in vertical blank.

This is the VBlank (vertical blank) signal used by the pipe and planes.

In particular, this causes the double-buffered pipe and plane registers to

update.

By default, the (unmodified) transcoder vertical blank always starts at the

end of the vertical active. If the transcoder's vertical blank start is set

to a value higher than vertical active, the pipe's vertical blank signal

starts later than the (modified) transcoder vertical blank.

Defined at line 753 of file ../../src/graphics/display/drivers/intel-display/registers-pipe.h

template <, >

typename SelfType::ValueType vblank ()