class MemoryAddressDecoderDimmParametersCometLake

Defined at line 624 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

MAD_DIMM_CH0_0_0_0_MCHBAR (Channel 0 DIMM Characteristics)

MAD_DIMM_CH1_0_0_0_MCHBAR (Channel 1 DIMM Characteristics)

Rocket Lake: 636761-004 Sections 3.2.39-3.2.40 pages 128-129

Tiger Lake U: 631122-003 Sections 3.2.41-3.2.42 pages 141-143

Tiger Lake H: 643524-003 Sections 3.2.9-3.2.10 pages 117-119

Ice Lake: 341078-004 Sections 3.2.38-3.2.39 pages 131-132

Comet Lake: 615212-003 Sections 8.36-8.37 pages 194-196

Public Members

 field_RsvdZ_634

 field_ddr5_capacity_is_8gb_643

 field_swap_channel_address_bits_6_11_649

 field_dimm_s_built_from_8gb_modules_658

 field_dimm_s_rank_count_minus_1_663

 field_dimm_s_ddr_chip_width_select_666

 field_RsvdZ_668

 field_dimm_s_size_512mb_671

 field_RsvdZ_673

 field_dimm_l_built_from_8gb_modules_682

 field_dimm_l_rank_count_minus_1_687

 field_dimm_l_ddr_chip_width_select_689

 field_dimm_l_size_512mb_692

Public Methods

template <, >

typename SelfType::ValueType ddr5_capacity_is_8gb ()

If false, DDR5 capacity exceeds 8GB.

This bit must be false for non-DDR5 configurations.

This bit is only defined on Tiger Lake H, and is reserved MBZ (must be

zero) on all other platforms. This results in correct read semantics, as

the feature appears disabled on these platforms.

Defined at line 643 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_ddr5_capacity_is_8gb (typename SelfType::ValueType val)

If false, DDR5 capacity exceeds 8GB.

This bit must be false for non-DDR5 configurations.

This bit is only defined on Tiger Lake H, and is reserved MBZ (must be

zero) on all other platforms. This results in correct read semantics, as

the feature appears disabled on these platforms.

Defined at line 643 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_swap_channel_address_bits_6_11 (typename SelfType::ValueType val)

Selects how zone address bits feed into BG and CAS bits.

If this bit is true, channel address bit 6 becomes BG (bank group) bit 0,

and channel address bit 11 becomes CAS (column address) bit 7.

Defined at line 649 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType swap_channel_address_bits_6_11 ()

Selects how zone address bits feed into BG and CAS bits.

If this bit is true, channel address bit 6 becomes BG (bank group) bit 0,

and channel address bit 11 becomes CAS (column address) bit 7.

Defined at line 649 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_s_built_from_8gb_modules ()

If true, DIMM S is built from 8 GB DRAM modules.

This bit must be false on non-DDR3 configurations.

This bit is only defined on Comet Lake. It is reserved MBZ (must be zero)

on later memory controllers. This results in correct read semantics, as the

feature appears disabled on these platforms.

Defined at line 658 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_s_built_from_8gb_modules (typename SelfType::ValueType val)

If true, DIMM S is built from 8 GB DRAM modules.

This bit must be false on non-DDR3 configurations.

This bit is only defined on Comet Lake. It is reserved MBZ (must be zero)

on later memory controllers. This results in correct read semantics, as the

feature appears disabled on these platforms.

Defined at line 658 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_s_rank_count_minus_1 ()

The number of ranks in DIMM S. 0 = 1 rank, ... 3 = 4 ranks.

Values above 1 (2 ranks) are not valid for for DIMM S.

Defined at line 663 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_s_rank_count_minus_1 (typename SelfType::ValueType val)

The number of ranks in DIMM S. 0 = 1 rank, ... 3 = 4 ranks.

Values above 1 (2 ranks) are not valid for for DIMM S.

Defined at line 663 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

DdrChipWidthValue dimm_s_ddr_chip_width_select ()

The DDR chip width for DIMM S.

Defined at line 666 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_s_ddr_chip_width_select (DdrChipWidthValue val)

The DDR chip width for DIMM S.

Defined at line 666 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_s_size_512mb ()

Size of DIMM S in multiples of 0.5 GB (512 MB).

Defined at line 671 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_s_size_512mb (typename SelfType::ValueType val)

Size of DIMM S in multiples of 0.5 GB (512 MB).

Defined at line 671 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_l_built_from_8gb_modules ()

If true, DIMM L is built from 8 GB DRAM modules.

This bit must be false on non-DDR3 configurations.

This bit is only defined on Comet Lake. It is reserved MBZ (must be zero)

on later memory controllers. This results in correct read semantics, as the

feature appears disabled on these platforms.

Defined at line 682 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_l_built_from_8gb_modules (typename SelfType::ValueType val)

If true, DIMM L is built from 8 GB DRAM modules.

This bit must be false on non-DDR3 configurations.

This bit is only defined on Comet Lake. It is reserved MBZ (must be zero)

on later memory controllers. This results in correct read semantics, as the

feature appears disabled on these platforms.

Defined at line 682 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_l_rank_count_minus_1 ()

The number of ranks in DIMM L. 0 = 1 rank, 1 = 2 ranks ... 3 = 4 ranks.

Values above 1 (2 ranks) are only valid in ERM (Enhanced Rank Mode).

Defined at line 687 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_l_rank_count_minus_1 (typename SelfType::ValueType val)

The number of ranks in DIMM L. 0 = 1 rank, 1 = 2 ranks ... 3 = 4 ranks.

Values above 1 (2 ranks) are only valid in ERM (Enhanced Rank Mode).

Defined at line 687 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

DdrChipWidthValue dimm_l_ddr_chip_width_select ()

Defined at line 689 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_l_ddr_chip_width_select (DdrChipWidthValue val)

Defined at line 689 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType dimm_l_size_512mb ()

Size of DIMM L in multiples of 0.5 GB (512 MB).

Defined at line 692 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_dimm_l_size_512mb (typename SelfType::ValueType val)

Size of DIMM L in multiples of 0.5 GB (512 MB).

Defined at line 692 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_s_ddr_chip_width ()

The width of the DDR chips in DIMM S.

Defined at line 695 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_l_ddr_chip_width ()

The width of the DDR chips in DIMM L.

Defined at line 700 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_s_rank_count ()

The number of ranks in DIMM S.

Defined at line 705 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_l_rank_count ()

The number of ranks in DIMM L.

Defined at line 712 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_s_size_mb ()

The size of DIMM S, in MB.

Defined at line 719 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int dimm_l_size_mb ()

The size of DIMM L, in MB.

Defined at line 726 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

hwreg::RegisterAddr<MemoryAddressDecoderDimmParametersCometLake> GetForControllerAndChannel (int memory_controller_index, int channel_index)

Defined at line 732 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

hwreg::RegisterAddr<MemoryChannelTimingsTigerLake> GetForTigerLakeHControllerAndChannel (int memory_controller_index, int channel_index)

For Tiger Lake H SKUs.

`memory_controller_index` and `channel_index` are 0-based.

Defined at line 745 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

Enumerations

enum DdrChipWidthValue

Name	Value
kX8	0b00
kX16	0b01
kX32	0b10
kReserved	0b11

Defined at line 627 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h