class GMBusControllerInterruptMask

Defined at line 475 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

GMBUS4

(Graphic Management Bus Configuration Register 4 -- Interrupt Mask)

This register specifies the GMBUS events that can trigger a display

engine interrupt.

All reserved bits in this register are MBZ (must be zero). So, the register

can be safely updated without reading it first.

This register is written protected when `software_clear_interrupt` in

`GMBusCommand` (GMBUS1) register is enabled.

Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev 2.0 Part 1, Page 1029

Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1, Page 737

Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 1, Page 731

Public Members

 field_RsvdZ_478

 field_target_stall_timeout_interrupt_enabled_484

 field_nack_occurred_interrupt_enabled_490

 field_is_idle_interrupt_enabled_496

 field_is_waiting_interrupt_enabled_502

 field_is_ready_interrupt_enabled_508

Public Methods

template <, >

SelfType & set_target_stall_timeout_interrupt_enabled (typename SelfType::ValueType val)

If this bit is true, when `target_stall_timeout` bit in

`GMBusControllerStatus` (GMBUS2) register is asserted, the south display

engine will trigger an interrupt, and the `gmbus` bit in `SdeInterruptBase`

status register will be set to true.

Defined at line 484 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

typename SelfType::ValueType target_stall_timeout_interrupt_enabled ()

If this bit is true, when `target_stall_timeout` bit in

`GMBusControllerStatus` (GMBUS2) register is asserted, the south display

engine will trigger an interrupt, and the `gmbus` bit in `SdeInterruptBase`

status register will be set to true.

Defined at line 484 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

typename SelfType::ValueType nack_occurred_interrupt_enabled ()

If this bit is true, when `nack_occurred` bit in `GMBusControllerStatus`

(GMBUS2) register is asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 490 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

SelfType & set_nack_occurred_interrupt_enabled (typename SelfType::ValueType val)

If this bit is true, when `nack_occurred` bit in `GMBusControllerStatus`

(GMBUS2) register is asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 490 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

typename SelfType::ValueType is_idle_interrupt_enabled ()

If this bit is true, when `is_active` bit in `GMBusControllerStatus`

(GMBUS2) register is de-asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 496 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

SelfType & set_is_idle_interrupt_enabled (typename SelfType::ValueType val)

If this bit is true, when `is_active` bit in `GMBusControllerStatus`

(GMBUS2) register is de-asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 496 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

typename SelfType::ValueType is_waiting_interrupt_enabled ()

If this bit is true, when `is_waiting` bit in `GMBusControllerStatus`

(GMBUS2) register is asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 502 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

SelfType & set_is_waiting_interrupt_enabled (typename SelfType::ValueType val)

If this bit is true, when `is_waiting` bit in `GMBusControllerStatus`

(GMBUS2) register is asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 502 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

typename SelfType::ValueType is_ready_interrupt_enabled ()

If this bit is true, when `is_ready` bit in `GMBusControllerStatus`

(GMBUS2) register is asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 508 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

template <, >

SelfType & set_is_ready_interrupt_enabled (typename SelfType::ValueType val)

If this bit is true, when `is_ready` bit in `GMBusControllerStatus`

(GMBUS2) register is asserted, the south display engine will trigger an

interrupt, and the `gmbus` bit in `SdeInterruptBase` status register will

be set to true.

Defined at line 508 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h

hwreg::RegisterAddr<GMBusControllerInterruptMask> Get ()

Defined at line 510 of file ../../src/graphics/display/drivers/intel-display/registers-gmbus.h