class ArbitrationControl
Defined at line 28 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ARB_CTL (Display Arbitration Control 1)
This register has bits that are reserved but not MBZ (must be zero). So, it
can only be safely updated via read-modify-write operations.
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev2.0 Part 1 pages 51-53
DG1: IHD-OS-DG1-Vol 2c-2.21 Part 1 pages 13-15
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 82-83
Skylake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 81-82
Public Members
field_framebuffer_compression_writes_wake_memory_31 field_RsvdZ_33 field_high_priority_queue_watermark_bits_40 field_low_priority_back_to_back_request_limit_bits_47 field_translation_lookaside_buffer_request_limit_55 field_translation_lookaside_buffer_in_flight_request_limit_63 field_framebuffer_compression_watermarks_disabled_66 field_tiled_address_swizzling_75 field_high_priority_request_chain_page_break_limit_80 field_RsvdZ_82 field_high_priority_request_chain_cache_line_limit_88Public Methods
template <, >typename SelfType::ValueType framebuffer_compression_writes_wake_memory ()If true, writes to FBC (framebuffer compression) surfaces wake up RAM.
Defined at line 31 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_framebuffer_compression_writes_wake_memory (typename SelfType::ValueType val)If true, writes to FBC (framebuffer compression) surfaces wake up RAM.
Defined at line 31 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType high_priority_queue_watermark_bits ()The HP (high-priority) queue is read after it has this many entries.
This field has a non-trivial encoding. It should be used via the
`high_priority_queue_watermark()` and `set_high_priority_queue_watermark()`
helpers.
Defined at line 40 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_high_priority_queue_watermark_bits (typename SelfType::ValueType val)The HP (high-priority) queue is read after it has this many entries.
This field has a non-trivial encoding. It should be used via the
`high_priority_queue_watermark()` and `set_high_priority_queue_watermark()`
helpers.
Defined at line 40 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType low_priority_back_to_back_request_limit_bits ()Maximum number of LP (low-priority) write requests accepted from a client.
This field has a non-trivial encoding. It should be used via the
`low_priority_back_to_back_request_limit()` and
`set_low_priority_back_to_back_request_limit()` helpers.
Defined at line 47 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_low_priority_back_to_back_request_limit_bits (typename SelfType::ValueType val)Maximum number of LP (low-priority) write requests accepted from a client.
This field has a non-trivial encoding. It should be used via the
`low_priority_back_to_back_request_limit()` and
`set_low_priority_back_to_back_request_limit()` helpers.
Defined at line 47 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_translation_lookaside_buffer_request_limit (typename SelfType::ValueType val)Maximum number of TLB requests issued in one arbitration loop.
This limit applies to TLB (translation lookaside buffer) and VT-D
(virtualized directed I/O) address translation requests.
This value must not be zero.
Defined at line 55 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType translation_lookaside_buffer_request_limit ()Maximum number of TLB requests issued in one arbitration loop.
This limit applies to TLB (translation lookaside buffer) and VT-D
(virtualized directed I/O) address translation requests.
This value must not be zero.
Defined at line 55 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_translation_lookaside_buffer_in_flight_request_limit (typename SelfType::ValueType val)Maximum number of TLB requests in-flight.
This limit applies to TLB (translation lookaside buffer) and VT-D
(virtualized directed I/O) address translation requests.
This value must not be zero.
Defined at line 63 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType translation_lookaside_buffer_in_flight_request_limit ()Maximum number of TLB requests in-flight.
This limit applies to TLB (translation lookaside buffer) and VT-D
(virtualized directed I/O) address translation requests.
This value must not be zero.
Defined at line 63 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType framebuffer_compression_watermarks_disabled ()If true, the FBC (framebuffer compression) watermarks are disabled.
Defined at line 66 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_framebuffer_compression_watermarks_disabled (typename SelfType::ValueType val)If true, the FBC (framebuffer compression) watermarks are disabled.
Defined at line 66 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_tiled_address_swizzling (typename SelfType::ValueType val)Zero on all supported display engines.
This field was used to configure Display Engine-side swizzling of physical
memory address bits when accessing Y-tiled surfaces. On recent processors,
this feature has been deprecated in favor of DRAM controller-level address
swizzling, and the field should be set to 0 indicating no display requests
address swizzling on these processors.
Defined at line 75 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType tiled_address_swizzling ()Zero on all supported display engines.
This field was used to configure Display Engine-side swizzling of physical
memory address bits when accessing Y-tiled surfaces. On recent processors,
this feature has been deprecated in favor of DRAM controller-level address
swizzling, and the field should be set to 0 indicating no display requests
address swizzling on these processors.
Defined at line 75 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType high_priority_request_chain_page_break_limit ()Maximum number of page breaks in a chain of HP (high-priority) requests.
This value must not be zero.
Defined at line 80 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_high_priority_request_chain_page_break_limit (typename SelfType::ValueType val)Maximum number of page breaks in a chain of HP (high-priority) requests.
This value must not be zero.
Defined at line 80 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >typename SelfType::ValueType high_priority_request_chain_cache_line_limit ()Maximum number of cachelines in a chain of HP (high-priority) requests.
This value must be greater than 8, which is the size of a DBUF (Display
Buffer) block.
Defined at line 88 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
template <, >SelfType & set_high_priority_request_chain_cache_line_limit (typename SelfType::ValueType val)Maximum number of cachelines in a chain of HP (high-priority) requests.
This value must be greater than 8, which is the size of a DBUF (Display
Buffer) block.
Defined at line 88 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t high_priority_queue_watermark ()Maximum number of LP (low-priority) write requests accepted from a client.
Defined at line 91 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl & set_high_priority_queue_watermark (int32_t watermark)See `high_priority_queue_watermark()` for details.
Defined at line 98 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
int32_t low_priority_back_to_back_request_limit ()Maximum number of LP (low-priority) write requests accepted from a client.
After a client reaches this limit of back-to-back requests, re-arbitration
occurs.
Defined at line 110 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
ArbitrationControl & set_low_priority_back_to_back_request_limit (int32_t request_limit)See `low_priority_back_to_back_request_limit()` for details.
Defined at line 117 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
hwreg::RegisterAddr<ArbitrationControl> GetForArbiter (int arbiter_index)`arbiter_index` zero (0) represents the global arbiter. The following
indexes represent the numbered arbiters.
Kaby Lake and Skylake only have a global arbiter.
Defined at line 126 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h
uint32_t TwoBitLog2 (int32_t value)Helper for setting 2-bit fields that use log2 representation.
Defined at line 137 of file ../../src/graphics/display/drivers/intel-display/registers-arbiter.h