class PchBacklightFreqDuty

Defined at line 75 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

SBLC_PWM_CTL2 (South / PCH Backlight Control 2)

Does not exist on DG1 or Tiger Lake. The MMIO address is recycled for the new

SLBC_PWM_FREQ register. The PWM frequency and duty cycle are specified in the

SLBC_PWM_FREQ and SLBC_PWM_DUTY registers.

Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 2 page 788

Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 2 page 773

Public Members

 field_freq_divider_81

 field_duty_cycle_85

template <, >

typename SelfType::ValueType freq_divider ()

Based on the frequency of the clock and desired PWM frequency.

PWM frequency = RAWCLK_FREQ / (freq_divider * backlight_pwm_multiplier)

backlight_pwm_multiplier is 16 or 128, based on SCHICKEN_1.

Defined at line 81 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_freq_divider (typename SelfType::ValueType val)

Based on the frequency of the clock and desired PWM frequency.

PWM frequency = RAWCLK_FREQ / (freq_divider * backlight_pwm_multiplier)

backlight_pwm_multiplier is 16 or 128, based on SCHICKEN_1.

Defined at line 81 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

typename SelfType::ValueType duty_cycle ()

Must be

= `freq_divider`.

0 = 0% PWM duty cycle. `freq_divider` = 100% PWM duty cycle.

Defined at line 85 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

template <, >

SelfType & set_duty_cycle (typename SelfType::ValueType val)

Must be

= `freq_divider`.

0 = 0% PWM duty cycle. `freq_divider` = 100% PWM duty cycle.

Defined at line 85 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h

hwreg::RegisterAddr<PchBacklightFreqDuty> Get ()

Defined at line 87 of file ../../src/graphics/display/drivers/intel-display/registers-pch.h