class GMBusClockPortSelect

This selects the clock rate of the serial bus, i.e. the I2C protocol clock

when drivers use GMBUS for data transfer. It defines the AC timing

parameters used for different bus rates / I2C bus mode.

This field must only be changed when the `is_active` field in

`GMBusControllerStatus` (GMBUS2) register is false, i.e. the GMBUS is idle.

Note that this only changes the clock rate when transferring data using

GMBUS protocol. If drivers implements software-based bit banging using the

raw GPIO pins, they don't need to follow the bus rate.

This selects the clock rate of the serial bus, i.e. the I2C protocol clock

when drivers use GMBUS for data transfer. It defines the AC timing

parameters used for different bus rates / I2C bus mode.

This field must only be changed when the `is_active` field in

`GMBusControllerStatus` (GMBUS2) register is false, i.e. the GMBUS is idle.

Note that this only changes the clock rate when transferring data using

GMBUS protocol. If drivers implements software-based bit banging using the

raw GPIO pins, they don't need to follow the bus rate.

This field overrides the `total_byte_count` field on `GMBusCommand`

(GMBUS1) register. When this bit is enabled, the device will allow burst

reads greater than 511 bytes.

On Tiger Lake, this feature is supported.

On Skylake, this feature is not supported and the bit must be zero.

The underlying feature is not implemented on some PCH chipsets used with

Kaby Lake display engines. The models are listed in IHD-OS-KBL-Vol 12-1.17

section "Sequence for GMBUS Burst Reads Greater Than 511 Bytes", page 199.

This field overrides the `total_byte_count` field on `GMBusCommand`

(GMBUS1) register. When this bit is enabled, the device will allow burst

reads greater than 511 bytes.

On Tiger Lake, this feature is supported.

On Skylake, this feature is not supported and the bit must be zero.

The underlying feature is not implemented on some PCH chipsets used with

Kaby Lake display engines. The models are listed in IHD-OS-KBL-Vol 12-1.17

section "Sequence for GMBUS Burst Reads Greater Than 511 Bytes", page 199.

In Intel Display Engine, every DDI is allocated a pair of numbered GPIO

pins for I2C / GMBUS communication.

This field selects a GMBUS pin pair for use in the GMBUS communication.

The DDI

<

-> pin pair mapping varies by platform. The mapping is available

at: Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev 2.0 Part 1, Page 1020 Kaby Lake:

IHD-OS-KBL-Vol 2c-1.17 Part 1, Page 728 Skylake: IHD-OS-SKL-Vol 2c-05.16

Part 1, Page 723

Note that the GMBUS pin pair ID may not be equal to the GPIO pin pair ID.

Note: On Skylake and Kaby Lake, only bits 2:0 are defined for this field

but bits 4:3 are reserved as "must be zero"; for compatibility we use the

same field definition across platforms, but the highest two bits on Skylake

and Kaby Lake will always be zero.

In Intel Display Engine, every DDI is allocated a pair of numbered GPIO

pins for I2C / GMBUS communication.

This field selects a GMBUS pin pair for use in the GMBUS communication.

The DDI

<

-> pin pair mapping varies by platform. The mapping is available

at: Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev 2.0 Part 1, Page 1020 Kaby Lake:

IHD-OS-KBL-Vol 2c-1.17 Part 1, Page 728 Skylake: IHD-OS-SKL-Vol 2c-05.16

Part 1, Page 723

Note that the GMBUS pin pair ID may not be equal to the GPIO pin pair ID.

Note: On Skylake and Kaby Lake, only bits 2:0 are defined for this field

but bits 4:3 are reserved as "must be zero"; for compatibility we use the

same field definition across platforms, but the highest two bits on Skylake

and Kaby Lake will always be zero.

Helper to select typed `pin_pair` for GMBUS communication.