class MemoryChannelTimingsAlderLake
Defined at line 87 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
TC_PRE_0_0_0_MCHBAR (PRE Command Timing)
Raptor Lake: 743846-001 Section 3.2.70 pages 143-144
Alder Lake S: 655259-003 Section 3.2.66 pages 126-127
Alder Lake H: 710723-003 Section 3.2.66 pages 155-156
Public Members
field_RsvdZ_90 field_derating_extensions_95 field_t_rcd_104 field_t_ras_109 field_t_wrpre_114 field_t_rcdw_120 field_t_ppd_127 field_t_rdpre_132 field_t_rpab_ext_139 field_t_rp_144Public Methods
template <, >typename SelfType::ValueType derating_extensions ()Value added to DRAM timings when the LPDDR dimm is hot.
This field must be zero for non-LP (Low-Power) DDR.
Defined at line 95 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_derating_extensions (typename SelfType::ValueType val)Value added to DRAM timings when the LPDDR dimm is hot.
This field must be zero for non-LP (Low-Power) DDR.
Defined at line 95 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_rcd (typename SelfType::ValueType val)tRCD DDR timing parameter.
The minimum delay between ACT and CAS in the same bank.
On LPDDR5x, this delay only applies to RD (read) CAS, and the minimum delay
between ACT and WR (write) CAS is specified separately the `t_rcdw` field.
On other technologies, this delay applies to both RD and WR.
Defined at line 104 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_rcd ()tRCD DDR timing parameter.
The minimum delay between ACT and CAS in the same bank.
On LPDDR5x, this delay only applies to RD (read) CAS, and the minimum delay
between ACT and WR (write) CAS is specified separately the `t_rcdw` field.
On other technologies, this delay applies to both RD and WR.
Defined at line 104 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_ras (typename SelfType::ValueType val)tRAS DDR timing parameter.
The minimum delay between ACT and PRE in the same bank.
Defined at line 109 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_ras ()tRAS DDR timing parameter.
The minimum delay between ACT and PRE in the same bank.
Defined at line 109 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_wrpre (typename SelfType::ValueType val)tWRPRE DDR timing parameter.
The minimum delay between WR and PRE in the same bank.
Defined at line 114 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_wrpre ()tWRPRE DDR timing parameter.
The minimum delay between WR and PRE in the same bank.
Defined at line 114 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_rcdw (typename SelfType::ValueType val)t_RCDW DDR timing parameter.
The minimum delay between ACT and CAS WR in the same bank. This delay is
only relevant in LPDDR5x configurations.
Defined at line 120 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_rcdw ()t_RCDW DDR timing parameter.
The minimum delay between ACT and CAS WR in the same bank. This delay is
only relevant in LPDDR5x configurations.
Defined at line 120 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_ppd (typename SelfType::ValueType val)tPPD DDR timing parameter.
The minimum delay between PRE/PREALL commands in the same rank.
This field is not used in DDR5 configurations.
Defined at line 127 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_ppd ()tPPD DDR timing parameter.
The minimum delay between PRE/PREALL commands in the same rank.
This field is not used in DDR5 configurations.
Defined at line 127 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_rdpre (typename SelfType::ValueType val)tRDPRE DDR timing parameter.
The minimum delay between RD and PRE commands in the same bank.
Defined at line 132 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_rdpre ()tRDPRE DDR timing parameter.
The minimum delay between RD and PRE commands in the same bank.
Defined at line 132 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_rpab_ext (typename SelfType::ValueType val)tRPab - tRBpb LPDDR timing parameter value.
The difference between the minimum delay between PREALL and ACT and the
minimum delay between PRE and ACT. Must be zero for DDR, because only LPDDR
allows this difference.
Defined at line 139 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_rpab_ext ()tRPab - tRBpb LPDDR timing parameter value.
The difference between the minimum delay between PREALL and ACT and the
minimum delay between PRE and ACT. Must be zero for DDR, because only LPDDR
allows this difference.
Defined at line 139 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_t_rp (typename SelfType::ValueType val)tRP DDR timing parameter.
The minimum delay between PRE and ACT in the same bank.
Defined at line 144 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >typename SelfType::ValueType t_rp ()tRP DDR timing parameter.
The minimum delay between PRE and ACT in the same bank.
Defined at line 144 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
hwreg::RegisterAddr<MemoryChannelTimingsAlderLake> GetForControllerAndChannel (int memory_controller_index, int channel_index)Defined at line 146 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h