class MemoryAddressDecoderInterChannelConfigIceLake

Defined at line 322 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

MAD_INTER_CHANNEL_0_0_0_MCHBAR (Inter-Channel Decode Parameters).

Raptor Lake: 743846-001 Section 3.2.46 pages 126-127

Alder Lake S: 655259-003 Section 3.2.42 pages 107-108

Alder Lake H: 710723-003 Section 3.2.42 pages 136-137

Rocket Lake: 636761-004 Section 3.2.36 pages 125-126

Tiger Lake U: 631122-003 Section 3.2.38 pages 139-140

Tiger Lake H: 643524-003 Section 3.2.6 pages 115-116

Ice Lake: 341078-004 Section 3.2.35 pages 128-129

Public Members

 field_half_cacheline_mode_enabled_348

 field_RsvdZ_350

 field_channel_width_select_tiger_lake_354

 field_RsvdZ_356

 field_channel_s_size_512_361

 field_RsvdZ_363

 field_channel_l_is_physical_channel1_366

 field_enhanced_channel_mode_376

 field_ddr_type_select_379

Public Methods

template <, >

typename SelfType::ValueType half_cacheline_mode_enabled ()

If true, the memory controller operates on 32-byte requests.

By default, the memory controller operates on 64-byte cache lines.

This field is not defined on some platforms (Rocket Lake, Ice Lake, Comet

Lake). The underlying bit is reserved MBZ (must be zero). This results in

correct read semantics, as the feature appears disabled on these platforms.

Defined at line 348 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_half_cacheline_mode_enabled (typename SelfType::ValueType val)

If true, the memory controller operates on 32-byte requests.

By default, the memory controller operates on 64-byte cache lines.

This field is not defined on some platforms (Rocket Lake, Ice Lake, Comet

Lake). The underlying bit is reserved MBZ (must be zero). This results in

correct read semantics, as the feature appears disabled on these platforms.

Defined at line 348 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

ChannelWidthTigerLakeValue channel_width_select_tiger_lake ()

This field is not documented on some platforms (Ice Lake, Comet Lake). The

underlying bits are MBZ (must be zero).

Defined at line 354 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_channel_width_select_tiger_lake (ChannelWidthTigerLakeValue val)

This field is not documented on some platforms (Ice Lake, Comet Lake). The

underlying bits are MBZ (must be zero).

Defined at line 354 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType channel_s_size_512 ()

The size of Channel S in 512MB units.

Valid values are 0-128.

Defined at line 361 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_channel_s_size_512 (typename SelfType::ValueType val)

The size of Channel S in 512MB units.

Valid values are 0-128.

Defined at line 361 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType channel_l_is_physical_channel1 ()

If false, Channel L is the physical channel 0.

Defined at line 366 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_channel_l_is_physical_channel1 (typename SelfType::ValueType val)

If false, Channel L is the physical channel 0.

Defined at line 366 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType enhanced_channel_mode ()

If true, the channel operates as two 32-bit channels.

This field should only be set to true in LPDDR4 configurations. By default,

LPDDR4 has a single 64-bit channel.

This bit is reserved MBZ (must be zero) on some platforms (Raptor Lake,

Alder Lake, Tiger Lake). This gives us the right read semantics, as the

feature appears disabled on these platforms.

Defined at line 376 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_enhanced_channel_mode (typename SelfType::ValueType val)

If true, the channel operates as two 32-bit channels.

This field should only be set to true in LPDDR4 configurations. By default,

LPDDR4 has a single 64-bit channel.

This bit is reserved MBZ (must be zero) on some platforms (Raptor Lake,

Alder Lake, Tiger Lake). This gives us the right read semantics, as the

feature appears disabled on these platforms.

Defined at line 376 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

DdrTypeValue ddr_type_select ()

The type of DDR memory installed in the system.

Defined at line 379 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_ddr_type_select (DdrTypeValue val)

The type of DDR memory installed in the system.

Defined at line 379 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

hwreg::RegisterAddr<MemoryAddressDecoderInterChannelConfigIceLake> GetForController (int memory_controller_index)

For Rocket Lake, Tiger Lake U/H35, and Ice Lake.

`memory_controller_index` is 0-based. Rocket Lake and Ice Lake processors

have a single memory controller.

Defined at line 385 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

hwreg::RegisterAddr<MemoryAddressDecoderInterChannelConfigIceLake> GetForAlderLakeController (int memory_controller_index)

For Raptor Lake, Alder Lake, and Tiger Lake H.

`memory_controller_index` is 0-based

Defined at line 403 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

Enumerations

enum ChannelWidthTigerLakeValue

Name	Value
kX16	0b00
kX32	0b01
kX64	0b10
kReserved	0b11

Documented values for `channel_width_select`.

Defined at line 326 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

enum DdrTypeValue

Name	Value
kDoubleDataRam4	0
kDoubleDataRam5	1
kLowPowerDoubleDataRam5	2
kLowPowerDoubleDataRam4	3

Documented values for `ddr_type_select`.

Defined at line 334 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h