class MemoryControllerBiosDataSkylake
Defined at line 1057 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
MC_BIOS_DATA_0_0_0_MCHBAR_PCU (Memory Controller BIOS Data)
The Kaby Lake and Skylake datasheets only document the
PCU_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PCU register, which has the same semantics as
the MC_BIOS_REQ_0_0_0_MCHBAR_PCU register in the Ice Lake and Tiger Lake
datasheets. The MC_BIOS_REQ_0_0_0_MCHBAR_PCU (Memory Controller BIOS Request)
register carries the latest request from the software to the memory
controller, whereas this register (Memory Controller BIOS Data) represents
the last request issued by the MRC (Memory Reference Code).
Comet Lake: 615212-003 Section 9.40 pages 238-239
Coffee Lake: 337345-003 Section 7.91 pages 237-238
Whiskey Lake: 338024-001 Section 7.60 pages 192-193
Amber Lake: 334662-005 Sections 6.83 pages 197-198
Kaby Lake S: 335196-002 Section 7.83 pages 229-230
Kaby Lake H: 335191-003 Section 7.91 pages 239-240
Skylake U: 332991-003 Section 7.83 pages 230-231
Skylake S: 332688-003 Section 7.83 pages 206-207
Skylake H: 332987-003 Section 7.83 pages 230-231
Public Members
field_controller_frequency_multiplier_1068Public Methods
template <, >typename SelfType::ValueType controller_frequency_multiplier ()The multipliers for the memory controller clock frequencies.
After the MRC (Memory Reference initialization Code) runs, the multiplier
should be greater than or equal to 3. A multiplier of 0 indicates that the
memory controller PLL will be shut down. Multipliers 1 and 2 are reserved.
The bases are 400/3 MHz for the memory controller's Dclk (double-clock) and
800/3 MHz for the memory controller's Qclk (quad-clock).
Defined at line 1068 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
template <, >SelfType & set_controller_frequency_multiplier (typename SelfType::ValueType val)The multipliers for the memory controller clock frequencies.
After the MRC (Memory Reference initialization Code) runs, the multiplier
should be greater than or equal to 3. A multiplier of 0 indicates that the
memory controller PLL will be shut down. Multipliers 1 and 2 are reserved.
The bases are 400/3 MHz for the memory controller's Dclk (double-clock) and
800/3 MHz for the memory controller's Qclk (quad-clock).
Defined at line 1068 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
int64_t controller_quad_clock_frequency_hz ()The memory controller's Qclk (quad-clock) frequency, in Hz.
Returns 0 if the memory controller PLL is disabled.
Defined at line 1073 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h
hwreg::RegisterAddr<MemoryControllerBiosDataSkylake> Get ()Defined at line 1082 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h