class PipeScalerPowerGateControl

Defined at line 1007 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

PS_PWR_GATE (Pipe Scaler Power Gate Control)

Controls the power gate for pipe scaler memory.

This register is double buffered. See PipeScalerWindowSize for arming and

dis-arming double-buffer updates.

This register has bits that are reserved but not MBZ (must be zero). So, it

can only be safely updated via read-modify-write operations.

Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev 2.0, Page 1014-1015

Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 2, Pages 657-658

Public Members

 field_RsvdZ_1012

 field_dynamic_power_gate_disabled_tiger_lake_1019

 field_filter_group_ram_settling_time_skylake_1030

 field_sleep_enable_delay_time_skylake_1041

static const uint32_t kBaseAddr

template <, >

typename SelfType::ValueType dynamic_power_gate_disabled_tiger_lake ()

Disables the dynamic power gate of unused memory embedded blocks (EBB)

when processing low resolution source images.

This bit is only available on Tiger Lake. On Kaby Lake and Skylake,

this bit must be zero.

Defined at line 1019 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

template <, >

SelfType & set_dynamic_power_gate_disabled_tiger_lake (typename SelfType::ValueType val)

Disables the dynamic power gate of unused memory embedded blocks (EBB)

when processing low resolution source images.

This bit is only available on Tiger Lake. On Kaby Lake and Skylake,

this bit must be zero.

Defined at line 1019 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

template <, >

FilterGroupRamSettlingTime filter_group_ram_settling_time_skylake ()

This field is only available on Kaby Lake and Skylake. On Tiger Lake, this

field is reserved.

Defined at line 1030 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

template <, >

SelfType & set_filter_group_ram_settling_time_skylake (FilterGroupRamSettlingTime val)

This field is only available on Kaby Lake and Skylake. On Tiger Lake, this

field is reserved.

Defined at line 1030 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

template <, >

SelfType & set_sleep_enable_delay_time_skylake (SleepEnableDelayTime val)

This field is only available on Kaby Lake and Skylake. On Tiger Lake, this

field is reserved.

Defined at line 1041 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

template <, >

SleepEnableDelayTime sleep_enable_delay_time_skylake ()

This field is only available on Kaby Lake and Skylake. On Tiger Lake, this

field is reserved.

Defined at line 1041 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

enum FilterGroupRamSettlingTime

Time for RAMs in a given filter group to settle after they are powered up.

Defined at line 1022 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h

enum SleepEnableDelayTime

Delay between sleep enables of individual banks of RAMs.

Defined at line 1033 of file ../../src/graphics/display/drivers/intel-display/registers-pipe-scaler.h