class MemoryControllerBiosDataIceLake

Defined at line 879 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

MC_BIOS_REQ_0_0_0_MCHBAR_PCU (Memory Controller BIOS Request)

MC_BIOS_DATA_0_0_0_MCHBAR_PCU (Memory Controller BIOS Data)

Raptor Lake: 743846-001 Sections 3.3.42-3.3.43 pages 202-204

Alder Lake S: 655259-003 Section 3.3.41-3.3.42 pages 184-187

Alder Lake H: 710723-003 Section 3.3.41-3.3.42 pages 213-216

Rocket Lake: 636761-004 Sections 3.3.45-3.3.46 pages 172-174

Tiger Lake U: 631122-003 Sections 3.3.44-3.3.45 pages 197-199

Tiger Lake H: 643524-003 Sections 3.3.45-3.3.46 pages 190-192

Ice Lake: 341078-004 Section 3.3.44-3.3.45 pages 177-179

Public Members

 field_request_pending_897

 field_data_transmit_rail_max_current_multiplier_904

 field_data_transmit_rail_voltage_multiplier_911

 field_ddr_phy_bus_clock_multiplier_shift_ice_lake_918

 field_RsvdZ_920

 field_ddr_phy_bus_clock_multiplier_shift_tiger_lake_928

 field_controller_frequency_base_select_931

 field_controller_frequency_multiplier_938

Public Methods

template <, >

typename SelfType::ValueType request_pending ()

If true, the PCU (power controller) has not yet applied this configuration.

The system firmware sets this bit to true when it writes a new value to

this register. The PCU firmware clears this bit after it applies the

requested configuration changes.

This bit is only meaningful for the MC_BIOS_REQ_0_0_0_MCHBAR_PCU (Memory

Controller BIOS Request) register. It must be zero in the

MC_BIOS_DATA_0_0_0_MCHBAR_PCU (Memory Controller BIOS Data) register.

Defined at line 897 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_request_pending (typename SelfType::ValueType val)

If true, the PCU (power controller) has not yet applied this configuration.

The system firmware sets this bit to true when it writes a new value to

this register. The PCU firmware clears this bit after it applies the

requested configuration changes.

This bit is only meaningful for the MC_BIOS_REQ_0_0_0_MCHBAR_PCU (Memory

Controller BIOS Request) register. It must be zero in the

MC_BIOS_DATA_0_0_0_MCHBAR_PCU (Memory Controller BIOS Data) register.

Defined at line 897 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType data_transmit_rail_max_current_multiplier ()

Sets IccMax (the maximum current) on the VDDQ_TX (DDR data transmit) rail.

The value is a multiplier with the base 250 mA.

This field is reserved MBZ (must be zero) on Ice Lake and Rocket Lake.

Defined at line 904 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_data_transmit_rail_max_current_multiplier (typename SelfType::ValueType val)

Sets IccMax (the maximum current) on the VDDQ_TX (DDR data transmit) rail.

The value is a multiplier with the base 250 mA.

This field is reserved MBZ (must be zero) on Ice Lake and Rocket Lake.

Defined at line 904 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType data_transmit_rail_voltage_multiplier ()

Sets the voltage on the VDDQ_TX (DDR data transmit) rail.

The value is a multiplier with the base 5mV.

This field is reserved MBZ (must be zero) on Ice Lake and Rocket Lake.

Defined at line 911 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_data_transmit_rail_voltage_multiplier (typename SelfType::ValueType val)

Sets the voltage on the VDDQ_TX (DDR data transmit) rail.

The value is a multiplier with the base 5mV.

This field is reserved MBZ (must be zero) on Ice Lake and Rocket Lake.

Defined at line 911 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType ddr_phy_bus_clock_multiplier_shift_ice_lake ()

Sets the DDR PHY bus clock relatively to the memory controller Qclk.

This field is reserved MBZ (must be zero) on Alder Lake and Tiger Lake.

Those platforms use the `ddr_phy_bus_clock_multiplier_shift_tiger_lake`

field with the same semantics.

Defined at line 918 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_ddr_phy_bus_clock_multiplier_shift_ice_lake (typename SelfType::ValueType val)

Sets the DDR PHY bus clock relatively to the memory controller Qclk.

This field is reserved MBZ (must be zero) on Alder Lake and Tiger Lake.

Those platforms use the `ddr_phy_bus_clock_multiplier_shift_tiger_lake`

field with the same semantics.

Defined at line 918 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType ddr_phy_bus_clock_multiplier_shift_tiger_lake ()

2-bit equivalent of `ddr_phy_bus_clock_multiplier_shift_ice_lake`.

0 = 1X multiplier, so the DDR bus matches Qclk. 1 = 2X multiplier, so the

DDR bus operates at 2x Qclk. 2 = 4x multiplier.

This field is reserved MBZ (must be zero) on Ice Lake and Rocket Lake.

Defined at line 928 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_ddr_phy_bus_clock_multiplier_shift_tiger_lake (typename SelfType::ValueType val)

2-bit equivalent of `ddr_phy_bus_clock_multiplier_shift_ice_lake`.

0 = 1X multiplier, so the DDR bus matches Qclk. 1 = 2X multiplier, so the

DDR bus operates at 2x Qclk. 2 = 4x multiplier.

This field is reserved MBZ (must be zero) on Ice Lake and Rocket Lake.

Defined at line 928 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

ControllerFrequencyBaseValue controller_frequency_base_select ()

The base for the memory controller Qclk (quad clock) frequency.

Defined at line 931 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_controller_frequency_base_select (ControllerFrequencyBaseValue val)

The base for the memory controller Qclk (quad clock) frequency.

Defined at line 931 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

typename SelfType::ValueType controller_frequency_multiplier ()

The multiplier for the memory controller Qclk (quad clock) frequency.

After the MRC (Memory Reference initialization Code) runs, the multiplier

should be greater than or equal to 3. A multiplier of 0 indicates that the

memory controller PLL will be shut down. Multipliers 1 and 2 are reserved.

Defined at line 938 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

template <, >

SelfType & set_controller_frequency_multiplier (typename SelfType::ValueType val)

The multiplier for the memory controller Qclk (quad clock) frequency.

After the MRC (Memory Reference initialization Code) runs, the multiplier

should be greater than or equal to 3. A multiplier of 0 indicates that the

memory controller PLL will be shut down. Multipliers 1 and 2 are reserved.

Defined at line 938 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int32_t data_transmit_rail_max_current_milliamps ()

The maximum Icc (current) on the VDD_TX (DDR data transmit) rail.

The return value is expressed in mA (milliamperes). A value of zero means

that the field is not populated.

Defined at line 944 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int32_t data_transmit_rail_voltage_millivolts ()

The voltage on the VDD_TX (DDR data transmit) rail.

The return value is expressed in mV (millivolts). A value of zero means

that the field is not populated.

Defined at line 958 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int ddr_phy_bus_clock_multiplier_shift ()

Sets the DDR PHY bus clock relatively to the memory controller Qclk.

This field is a multiplier is relative to the memory controller Qclk (quad

clock) frequency. The field value is represented in log2, so the multiplier

is 1

field_value.

Defined at line 972 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int64_t ddr_phy_bus_frequency_hz ()

The DDR PHY bus frequency, in Hz.

Returns 0 if the memory controller PLL is disabled, or if the register has

an invalid configuration.

Defined at line 983 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int64_t controller_quad_clock_frequency_hz ()

The memory controller's Qclk (quad-clock) frequency, in Hz.

Returns 0 if the memory controller PLL is disabled, or if the register has

an invalid configuration.

Defined at line 1004 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

int32_t controller_frequency_base_hz_x3 ()

The memory controller's base frequency in Hz, multiplied by 3.

Returns zero if the field is set to an undocumented value.

The unusual return convention follows the datasheet recommendation for

representing the memory controller's base frequency.

Defined at line 1022 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

hwreg::RegisterAddr<MemoryControllerBiosDataIceLake> Get ()

Defined at line 1032 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h

Enumerations

enum ControllerFrequencyBaseValue

Name	Value
k133Mhz	0b000
k100Mhz	0b001

Documented values for `memory_controller_frequency_base_select`.

Defined at line 883 of file ../../src/graphics/display/drivers/intel-display/registers-memory-controller.h