class PllEnable
Defined at line 1217 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
DPLL_ENABLE (DPLL Enable), LCPLL_CTL / WRPLL_CTL (LCPLL/WRPLL Control).
This class describes all the PLL enablement registers, as they have similar
layouts.
On Tiger Lake, this covers all the DPLL_ENABLE (* PLL Enable) registers.
* DPLL0_ENABLE, DPLL1_ENABLE, DPLL4_ENABLE - for DPLL0/1/4
* TBTPLL_ENABLE - for DPLL2
* MGPLL1_ENABLE ... MGPLL6_ENABLE - for MG and Dekel PLLs 1-6
On Kaby Lake and Skylake, this covers the following registers:
* LCPLL1_CTL / LCPLL2_CTL - LCPLL1/2 Control - for DPLL0/1
* WRPLL1_CTL / WRPLL2_CTL - WRPLL1/2 Control - for DPLL2/3
PLL enablement registers must not be changed while their corresponding PLLs
are in use.
On Kaby Lake and Skylake, all DPLLs can be used to drive DDIs. DPLL0 also
drives the core display clocks (CDCLK, CD2XCLK). LCPLL (DPLL0, DPLL1)
probably stands for "LC-tank PLL" and WRPLL (DPLL2, DPLL3) probably means
"Wide-Range PLL". The distinction is historical, alluding to the LCPLLs and
WRPLLs on Broadwell (IHD-OS-BDW-Vol 11-11.15 page 110) and Haswell
(intel-gfx-prm-osrc-hsw-display Vol 11a dated 12/18/2013 page 191),
which support different ranges of output frequencies.
On Tiger Lake, TC (USB Type-C connector) DDI has its own PLL, called an MG
PLL. DPLLs (Display PLLs) 0, 1, and 4 can be connected to all DDIs. DPLL2 is
dedicated to generating the frequencies needed for TBT (Thunderbolt)
operation, and is shared by all DDIs that operate in Thunderbolt mode.
DPLL_ENABLE documentation:
Tiger Lake: IHD-OS-TGL-Vol 2c-1.22-Rev 2.0 Part 1 pages 656-657
LCPLL1_CTL and LCPLL2_CTL documentation:
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 1 pages 1121, 1122
Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 1 pages 1110, 1111
WRPLL1_CTL and WRPLL2_CTL documentation:
Kaby Lake: IHD-OS-KBL-Vol 2c-1.17 Part 2 pages 1349-1350
Skylake: IHD-OS-SKL-Vol 2c-05.16 Part 2 pages 1321-1322
Public Members
field_pll_enabled_1222 field_pll_locked_tiger_lake_and_lcpll1_1236 field_power_on_request_tiger_lake_1244 field_powered_on_tiger_lake_1252Public Methods
template <, >typename SelfType::ValueType pll_enabled ()If true, the PLL will be enabled. If false, the PLL will be disabled.
The PLL's frequency must be set before it is enabled.
Defined at line 1222 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll_enabled (typename SelfType::ValueType val)If true, the PLL will be enabled. If false, the PLL will be disabled.
The PLL's frequency must be set before it is enabled.
Defined at line 1222 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType pll_locked_tiger_lake_and_lcpll1 ()If true, the PLL is locked. If false, the PLL is not locked.
On Tiger Lake, this field is supported on all PLL enablement registers.
On Kaby Lake and Skylake, this field is only supported on LCPLL1, which
drives DPLL0. The underlying bit is reserved on all other registers. On
LCPLL1, this field seems redundant with the DPLL0 locked field in the
DPLL_STATUS register. However, PRM explicitly asks us to check this field,
in "Sequences to Initialize Display" sub-sections "Initialize Sequence" and
"Un-initialize Sequence".
Kaby Lake: IHD-OS-KBL-Vol 12-1.17 pages 112-113
Skylake: IHD-OS-SKL-Vol 12-05.16 pages 110-111
Defined at line 1236 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_pll_locked_tiger_lake_and_lcpll1 (typename SelfType::ValueType val)If true, the PLL is locked. If false, the PLL is not locked.
On Tiger Lake, this field is supported on all PLL enablement registers.
On Kaby Lake and Skylake, this field is only supported on LCPLL1, which
drives DPLL0. The underlying bit is reserved on all other registers. On
LCPLL1, this field seems redundant with the DPLL0 locked field in the
DPLL_STATUS register. However, PRM explicitly asks us to check this field,
in "Sequences to Initialize Display" sub-sections "Initialize Sequence" and
"Un-initialize Sequence".
Kaby Lake: IHD-OS-KBL-Vol 12-1.17 pages 112-113
Skylake: IHD-OS-SKL-Vol 12-05.16 pages 110-111
Defined at line 1236 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType power_on_request_tiger_lake ()If true, the PLL will eventually be powered on.
This field is only documented for Tiger Lake.
On Kaby Lake and Skylake, the underlying bit is reserved, and PLLs can be
assumed to be powered on at all times.
Defined at line 1244 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_power_on_request_tiger_lake (typename SelfType::ValueType val)If true, the PLL will eventually be powered on.
This field is only documented for Tiger Lake.
On Kaby Lake and Skylake, the underlying bit is reserved, and PLLs can be
assumed to be powered on at all times.
Defined at line 1244 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >typename SelfType::ValueType powered_on_tiger_lake ()If true, the PLL is currently powered on.
A PLL must be powered on before it is enabled.
This field is only documented for Tiger Lake. The underlying bit is
reserved on Kaby Lake and Skylake.
Defined at line 1252 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
template <, >SelfType & set_powered_on_tiger_lake (typename SelfType::ValueType val)If true, the PLL is currently powered on.
A PLL must be powered on before it is enabled.
This field is only documented for Tiger Lake. The underlying bit is
reserved on Kaby Lake and Skylake.
Defined at line 1252 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
hwreg::RegisterAddr<PllEnable> GetForSkylakeDpll (intel_display::PllId pll_id)Defined at line 1254 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
hwreg::RegisterAddr<PllEnable> GetForTigerLakeDpll (intel_display::PllId pll_id)Tiger Lake: On IHD-OS-TGL-Vol 2c-1.22-Rev 2.0, Page 656, it mentions
that the MG register instances are used for Type-C in general, so they
can control Dekel PLLs as well (for example, MGPLL1_ENABLE controls
Dekel PLL Type-C Port 1).
Defined at line 1267 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h