struct
Defined at line 1236 of file ../../src/graphics/display/drivers/intel-display/registers-dpll.h
If true, the PLL is locked. If false, the PLL is not locked.
On Tiger Lake, this field is supported on all PLL enablement registers.
On Kaby Lake and Skylake, this field is only supported on LCPLL1, which
drives DPLL0. The underlying bit is reserved on all other registers. On
LCPLL1, this field seems redundant with the DPLL0 locked field in the
DPLL_STATUS register. However, PRM explicitly asks us to check this field,
in "Sequences to Initialize Display" sub-sections "Initialize Sequence" and
"Un-initialize Sequence".
Kaby Lake: IHD-OS-KBL-Vol 12-1.17 pages 112-113
Skylake: IHD-OS-SKL-Vol 12-05.16 pages 110-111
Public Members
Field field