class GMBusControllerStatus

This bit has NO effect on the hardware, and is only used as an indicator

for software to query and declare the usage of the GMBUS controller.

Drivers can poll and wait until `software_lock_acquired` becomes false

before using the GMBUS controller, and set this bit (grab the software

lock) so that other threads won't use it at the same time.

This bit is write-protected when `software_clear_interrupt` in

`GMBusCommand` (GMBUS1) register is enabled.

This bit has NO effect on the hardware, and is only used as an indicator

for software to query and declare the usage of the GMBUS controller.

Drivers can poll and wait until `software_lock_acquired` becomes false

before using the GMBUS controller, and set this bit (grab the software

lock) so that other threads won't use it at the same time.

This bit is write-protected when `software_clear_interrupt` in

`GMBusCommand` (GMBUS1) register is enabled.

True when the controller is in WAIT state after data read / write.

Once this bit is true, the driver can set `GMBusCommand` register to

generate a STOP cycle or continue reading / writing, which will de-assert

this bit.

True when the controller is in WAIT state after data read / write.

Once this bit is true, the driver can set `GMBusCommand` register to

generate a STOP cycle or continue reading / writing, which will de-assert

this bit.

True when the target device has stalled the target device acknowledgement

beyond the time limit.

This bit is only meaningful when `enable_timeout` bit is set to true in

`GMBusCommand` (GMBUS1) register.

The Programmer's Reference Manual doesn't mention how to reset the bit, but

it's possible that a controller local reset can reset it.

True when the target device has stalled the target device acknowledgement

beyond the time limit.

This bit is only meaningful when `enable_timeout` bit is set to true in

`GMBusCommand` (GMBUS1) register.

The Programmer's Reference Manual doesn't mention how to reset the bit, but

it's possible that a controller local reset can reset it.

If true, GMBUS hardware enters a "ready" state and will not perform any

operation until the software acts.

Certain actions should not be performed while this bit is false. For

example, the semantics of reading/writing the `GMBusData` register are more

complex when this bit is false.

This bit transitions from false to true when:

- GMBUS is waiting for the software to read/write the `GMBusData` register

in order to advance an I2C read/write transaction.

- A GMBUS cycle ended with a STOP.

- GMBUS completes the partial reset procedure initiated via the

`GMBusCommand` register.

This bit transitions from true to false when:

- A new I2C transaction over GMBUS is triggered.

- GMBUS partial reset is initiated via the `GMBusCommand` register.

This bit is also known as "hardware ready" (or HW_RDY) bit in Intel

Programmer's Reference Manual.

If true, GMBUS hardware enters a "ready" state and will not perform any

operation until the software acts.

Certain actions should not be performed while this bit is false. For

example, the semantics of reading/writing the `GMBusData` register are more

complex when this bit is false.

This bit transitions from false to true when:

- GMBUS is waiting for the software to read/write the `GMBusData` register

in order to advance an I2C read/write transaction.

- A GMBUS cycle ended with a STOP.

- GMBUS completes the partial reset procedure initiated via the

`GMBusCommand` register.

This bit transitions from true to false when:

- A new I2C transaction over GMBUS is triggered.

- GMBUS partial reset is initiated via the `GMBusCommand` register.

This bit is also known as "hardware ready" (or HW_RDY) bit in Intel

Programmer's Reference Manual.

True if the receiver device doesn't send an acknowledgement signal after a

data byte is transmitted, which means a "not acknowledge (NACK)" in I2C.

This bit can only be cleared by performing a reset via the `GMBusCommand`

(GMBUS1) register.

True if the receiver device doesn't send an acknowledgement signal after a

data byte is transmitted, which means a "not acknowledge (NACK)" in I2C.

This bit can only be cleared by performing a reset via the `GMBusCommand`

(GMBUS1) register.

True if the controller is in an active state, false if the controller is

in an idle state.

Active states are: START (including RESTART), ADDRESS, INDEX, DATA, WAIT

and STOP phase.

True if the controller is in an active state, false if the controller is

in an idle state.

Active states are: START (including RESTART), ADDRESS, INDEX, DATA, WAIT

and STOP phase.

Can be used to determine the number of bytes currently transmitted /

received by the GMBUS controller hardware. Controller sets it to zero at

the start of a GMBUS transaction data transfer and increments it after the

completion of each byte of the data phase.

Note that because reads have internal storage, the byte count on a read

operation may be ahead of the data that has been accepted from the data

register.

Can be used to determine the number of bytes currently transmitted /

received by the GMBUS controller hardware. Controller sets it to zero at

the start of a GMBUS transaction data transfer and increments it after the

completion of each byte of the data phase.

Note that because reads have internal storage, the byte count on a read

operation may be ahead of the data that has been accepted from the data

register.