Namespaces
Enumerations
enum PowerWellId| Name | Value |
|---|---|
| PG1 | 0 |
| PG2 | 1 |
| PG3 | 2 |
| PG4 | 3 |
| PG5 | 4 |
Defined at line 21 of file ../../src/graphics/display/drivers/intel-display/power.h
enum DdiId| Name | Value |
|---|---|
| DDI_A | 0 |
| DDI_B | 1 |
| DDI_C | 2 |
| DDI_D | 3 |
| DDI_E | 4 |
| DDI_TC_1 | DDI_D |
| DDI_TC_2 | 4 |
| DDI_TC_3 | 5 |
| DDI_TC_4 | 6 |
| DDI_TC_5 | 7 |
| DDI_TC_6 | 8 |
Defined at line 26 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
enum TranscoderId| Name | Value |
|---|---|
| TRANSCODER_A | 0 |
| TRANSCODER_B | 1 |
| TRANSCODER_C | 2 |
| TRANSCODER_EDP | 3 |
TODO(https://fxbug.dev/42060657): Support Transcoder D on Tiger Lake.
Defined at line 66 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
enum PipeId| Name | Value |
|---|---|
| PIPE_A | 0 |
| PIPE_B | 1 |
| PIPE_C | 2 |
| PIPE_INVALID | 3 |
TODO(https://fxbug.dev/42060657): Support Pipe D on Tiger Lake.
Defined at line 103 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
enum PllId| Name | Value |
|---|---|
| DPLL_INVALID | -1 |
| DPLL_0 | 0 |
| DPLL_1 | 1 |
| DPLL_2 | 2 |
| DPLL_3 | 3 |
| DPLL_TC_1 | 4 |
| DPLL_TC_2 | 5 |
| DPLL_TC_3 | 6 |
| DPLL_TC_4 | 7 |
| DPLL_TC_5 | 8 |
| DPLL_TC_6 | 9 |
Defined at line 138 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
enum PchPanelPowerState| Name | Value |
|---|---|
| kPoweredDown | 0 |
| kWaitingForPowerCycleDelay | 1 |
| kPoweringUp | 2 |
| kPoweredUp | 3 |
| kPoweringDown | 4 |
The state of the PCH panel power sequence subsystem.
`kPoweredUp` and `kPoweredDown` are stable states.
Setting the PCH panel power target to "on" will drive the panel through a
subset of the following states:
* `kPoweringDown` (if the power target was recently set to "off") ->
* `kPoweredDown` ->
* `kWaitingForPowerCycleDelay` (if the panel was recently powered off) ->
* `kPoweringUp` ->
* `kPoweredUp` - the target state.
Setting the PCH panel power target to "off" will drive the panel through a
subset of the following states:
* `kPoweringUp` (if the power target was recently set to "on") ->
* `kPoweredUp` ->
* `kPoweringDown` ->
* `kPoweredDown` - the target state.
Defined at line 215 of file ../../src/graphics/display/drivers/intel-display/pch-engine.h
Records
-
class AcpiMemoryRegion -
class AddedDisplayInfo -
class ComboDdiTigerLake -
class Controller -
class ControllerResources -
class CoreDisplayClock -
class CoreDisplayClockSkylake -
class CoreDisplayClockTigerLake -
class DdiAuxChannel -
class DdiAuxChannelConfig -
class DdiFlags -
class DdiManager -
class DdiManagerSkylake -
class DdiManagerTigerLake -
class DdiPhysicalLayer -
class DdiPllConfig -
class DdiReference -
class DdiSkylake -
class DekelPllTigerLake -
class DisplayDevice -
class DisplayPll -
class DisplayPllManager -
class DisplayPllTigerLake -
class DpAuxChannel -
class DpAuxChannelImpl -
class DpCapabilities -
class DpDisplay -
class DpllFrequencyDividerConfig -
class DpllManagerSkylake -
class DpllManagerTigerLake -
class DpllOscillatorConfig -
class DpllSkylake -
class DynamicFlexIoDisplayPortControllerSafeStateSettingsTest_GetRejectsComboDdi_Test -
class DynamicFlexIoDisplayPortControllerSafeStateSettingsTest_Getter_Test -
class DynamicFlexIoDisplayPortControllerSafeStateSettingsTest_SetSafeModeDisabledRejectsDdiFromDifferentFia_Test -
class DynamicFlexIoDisplayPortMainLinkLaneEnabledTest_EnabledDisplayPortLaneBitsRejectsDdisFromDifferentFia_Test -
class DynamicFlexIoDisplayPortMainLinkLaneEnabledTest_GetRejectsComboDdi_Test -
class DynamicFlexIoDisplayPortMainLinkLaneEnabledTest_Getter_Test -
class DynamicFlexIoDisplayPortMainLinkLaneEnabledTest_SetEnabledDisplayPortLaneBitsRejectsDdisFromDifferentFia_Test -
class DynamicFlexIoDisplayPortMainLinkLaneEnabledTest_SetterNotSupportComboDdi_Test -
class DynamicFlexIoDisplayPortMainLinkLaneEnabledTest_Setter_Test -
class DynamicFlexIoDisplayPortPhyModeStatusTest_GetRejectsComboDdi_Test -
class DynamicFlexIoDisplayPortPhyModeStatusTest_Getter_Test -
class DynamicFlexIoDisplayPortPhyModeStatusTest_PhyIsReadyRejectsDdiFromDifferentFia_Test -
class DynamicFlexIoPinAssignmentTest_GetRejectsComboDdi_Test -
class DynamicFlexIoPinAssignmentTest_Getter_Test -
class DynamicFlexIoPinAssignmentTest_PinAssignmentRejectDdiFromDifferentFia_Test -
class DynamicFlexIoScratchPadTest_GetRejectsComboDdi_Test -
class DynamicFlexIoScratchPadTest_Getter_Test -
class DynamicFlexIoScratchPadTest_HelperMethodsRejectDdiFromDifferentFia_Test -
class FakeBufferCollection -
class FakeBufferCollectionConfig -
class FakeDisplay -
class FuseConfig -
class GMBusI2c -
class GMBusPinPair -
class GpioPort -
class Gtt -
class GttRegion -
class GttRegionImpl -
class HardwareCommonTest -
class HardwareCommonTest_KabyLake_Test -
class HardwareCommonTest_Skylake_Test -
class HardwareCommonTest_TigerLake_Test -
class HdmiDisplay -
class IgdOpRegion -
class IntelDisplayDriver -
class Interrupts -
class MemorySubsystemInfo -
class MockAllocator -
class PchClockParameters -
class PchEngine -
class PchPanelParameters -
class PchPanelPowerTarget -
class PciConfigOpRegion -
class Pipe -
class PipeIteratorBase -
class PipeManager -
class PipeManagerSkylake -
class PipeManagerTest -
class PipeManagerTest_SkylakeAllocatePipe_Test -
class PipeManagerTest_SkylakeReclaimUsedPipe_Test -
class PipeManagerTigerLake -
class PipeSkylake -
class PipeTest -
class PipeTest_GetVsyncConfigStamp_Test -
class PipeTest_TiedTranscoderId_Test -
class PipeTigerLake -
class Power -
class PowerController -
class PowerControllerCommand -
class PowerTest -
class PowerTest_Skylake_AuxIo_Test -
class PowerTest_Skylake_PowerWell2_Test -
class PowerTest_TigerLake_DdiIo_Test -
class PowerTest_TigerLake_PowerWell_Test -
class PowerWellInfo -
class PowerWellRef -
class RegisterTypeCTest -
class RegisterTypeCTest_DekelLaneRegister_Test -
class RegisterTypeCTest_ReadWriteDekelRegister_Test -
class ToDisplayModeTest_DmtTiming_Test -
class TypeCDdiTigerLake -
class bios_data_blocks_header -
class block_header -
class buffer_allocation -
class ddi_config -
class edp_config -
class general_definitions -
class igd_opregion -
class lfp_backlight -
class lfp_backlight_entry -
class lvds_config -
class sci_interface -
class vbt_header
Functions
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display::Mode ToDisplayMode (const display::DisplayTiming & timing)Defined at line 15 of file ../../src/graphics/display/drivers/intel-display/display-timing-mode-conversion.h
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cpp20::span<const DdiId> GetDdiIds (uint16_t device_id)Get the list of DDIs supported by the device of |device_id|.
Defined at line 15 of file ../../src/graphics/display/drivers/intel-display/ddi.cc
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cpp20::span<const int8_t> DpllSupportedFrequencyDividersKabyLake ()Returns to the list of documented DCO frequency dividers in Display PLLs.
The span will remain valid for the lifetime of the process. The span's
elements will be sorted in ascending order.
The supported dividers are currently above 1 and below 110.
Defined at line 16 of file ../../src/graphics/display/drivers/intel-display/dpll-config.cc
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int get_tile_byte_width (display::ImageTilingType tiling)Defined at line 18 of file ../../src/graphics/display/drivers/intel-display/tiling.h
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template <typename T>std::pair<T, size_t> RoundToPageBoundaries (T region_start_address, size_t region_size)Defined at line 22 of file ../../src/graphics/display/drivers/intel-display/acpi-memory-region-util.h
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zx::result<fbl::Vector<uint8_t>> ReadExtendedEdid (ReadEdidBlockFunction read_edid_block)Defined at line 24 of file ../../src/graphics/display/drivers/intel-display/edid-reader.cc
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bool is_skl (uint16_t device_id)Defined at line 28 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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bool is_kbl (uint16_t device_id)Defined at line 30 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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cpp20::span<const int8_t> DpllSupportedFrequencyDividersTigerLake ()Returns to the list of documented DCO frequency dividers in Display PLLs.
The span will remain valid for the lifetime of the process. The span's
elements are not sorted in ascending order.
The supported dividers are currently above 1 and below 110.
Defined at line 32 of file ../../src/graphics/display/drivers/intel-display/dpll-config.cc
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bool is_tgl (uint16_t device_id)Defined at line 34 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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bool operator== (const DdiPllConfig & lhs, const DdiPllConfig & rhs)Defined at line 35 of file ../../src/graphics/display/drivers/intel-display/dpll.cc
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bool is_skl_u (uint16_t device_id)Defined at line 36 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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int get_tile_byte_size (display::ImageTilingType tiling)Defined at line 38 of file ../../src/graphics/display/drivers/intel-display/tiling.h
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bool operator!= (const DdiPllConfig & lhs, const DdiPllConfig & rhs)Defined at line 41 of file ../../src/graphics/display/drivers/intel-display/dpll.cc
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bool is_skl_y (uint16_t device_id)Defined at line 41 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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bool operator== (const PchClockParameters & lhs, const PchClockParameters & rhs)Defined at line 41 of file ../../src/graphics/display/drivers/intel-display/pch-engine.cc
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int get_tile_px_height (display::ImageTilingType tiling)Defined at line 42 of file ../../src/graphics/display/drivers/intel-display/tiling.h
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bool is_kbl_u (uint16_t device_id)Defined at line 43 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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DpllOscillatorConfig CreateDpllOscillatorConfigKabyLake (int32_t afe_clock_khz)Finds DPLL (Display PLL) DCO operating parameters that produce a frequency.
Returns zero frequencies if no suitable frequency can be found. The DCO
(Digitally-Controlled Oscillator) circuit has some operating constraints, and
it's impossible to produce some frequencies given these constraints.
`afe_clock_khz` is the desired frequency of the AFE (Analog Front-End) clock
coming out of the PLL, in kHz. This is the clock frequency given to DDIs that
use the PLL as their clock source.
The AFE clock frequency must be half of the link rate supported by the DDI,
because DDIs use both clock edges (rising and falling) to output bits. For
protocols that use 8b/10b coding, the AFE clock frequency is 5x the symbol
clock rate for each link lane.
Defined at line 43 of file ../../src/graphics/display/drivers/intel-display/dpll-config.cc
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bool operator!= (const PchClockParameters & lhs, const PchClockParameters & rhs)Defined at line 45 of file ../../src/graphics/display/drivers/intel-display/pch-engine.h
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uint32_t width_in_tiles (display::ImageTilingType tiling, int width, int bytes_per_pixel)Defined at line 46 of file ../../src/graphics/display/drivers/intel-display/tiling.h
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bool is_kbl_y (uint16_t device_id)Defined at line 48 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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bool is_tgl_u (uint16_t device_id)Defined at line 50 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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uint32_t height_in_tiles (display::ImageTilingType tiling, int height)Defined at line 51 of file ../../src/graphics/display/drivers/intel-display/tiling.h
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template <registers::Platform P>cpp20::span<const DdiId> DdiIds ()Defined at line 54 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
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bool is_test_device (uint16_t device_id)Defined at line 55 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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registers::Platform GetPlatform (uint16_t device_id)Defined at line 57 of file ../../src/graphics/display/drivers/intel-display/pci-ids.h
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bool operator== (const PchPanelParameters & lhs, const PchPanelParameters & rhs)Defined at line 80 of file ../../src/graphics/display/drivers/intel-display/pch-engine.cc
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template <registers::Platform P>cpp20::span<const TranscoderId> TranscoderIds ()Defined at line 91 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
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bool operator== (const PchPanelPowerTarget & lhs, const PchPanelPowerTarget & rhs)Defined at line 93 of file ../../src/graphics/display/drivers/intel-display/pch-engine.cc
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template <registers::Platform P>cpp20::span<const PipeId> PipeIds ()Defined at line 127 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
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bool operator!= (const PchPanelParameters & lhs, const PchPanelParameters & rhs)Defined at line 147 of file ../../src/graphics/display/drivers/intel-display/pch-engine.h
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DpllOscillatorConfig CreateDpllOscillatorConfigForHdmiTigerLake (int32_t afe_clock_khz)Defined at line 155 of file ../../src/graphics/display/drivers/intel-display/dpll-config.cc
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template <registers::Platform P>cpp20::span<const PllId> PllIds ()Defined at line 170 of file ../../src/graphics/display/drivers/intel-display/hardware-common.h
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bool operator!= (const PchPanelPowerTarget & lhs, const PchPanelPowerTarget & rhs)Defined at line 193 of file ../../src/graphics/display/drivers/intel-display/pch-engine.h
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DpllOscillatorConfig CreateDpllOscillatorConfigForDisplayPortTigerLake (int32_t afe_clock_khz)Defined at line 226 of file ../../src/graphics/display/drivers/intel-display/dpll-config.cc
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DpllFrequencyDividerConfig CreateDpllFrequencyDividerConfigKabyLake (int8_t dco_divider)Finds a DPLL frequency divider configuration that produces `dco_divider`.
`dco_divider` must be an element of `DpllSupportedFrequencyDividers()`.
Defined at line 242 of file ../../src/graphics/display/drivers/intel-display/dpll-config.cc
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DpllFrequencyDividerConfig CreateDpllFrequencyDividerConfigTigerLake (int8_t dco_divider)Defined at line 299 of file ../../src/graphics/display/drivers/intel-display/dpll-config.cc
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zx_koid_t GetKoid (zx_handle_t handle)Defined at line 2124 of file ../../src/graphics/display/drivers/intel-display/intel-display.cc