class DisplayPllTigerLake

Defined at line 277 of file ../../src/graphics/display/drivers/intel-display/dpll.h

Display PLL (DPLL) for Tiger Lake display engines.

DPLLs are shareable across Combo PHYs. Multiple PHYs can use the same DPLL,

as long as they require the same frequency and SSC (Spread-Spectrum Clocking)

characteristics.

Public Methods

void ~DisplayPllTigerLake ()

Defined at line 280 of file ../../src/graphics/display/drivers/intel-display/dpll.h

void DisplayPllTigerLake (fdf::MmioBuffer * mmio_space, PllId pll_id)

Defined at line 463 of file ../../src/graphics/display/drivers/intel-display/dpll.cc

display::ScopedValueChange<int> OverrideLockWaitTimeoutUsForTesting (int timeout_us)

Tests that simulate retries must use the overrides below to avoid flakiness

stemming from scheduling variability. Tests that simulate timeouts should

use the overrides below to get the DisplayPllTigerLake to issue a

deterministic MMIO access pattern.

Defined at line 535 of file ../../src/graphics/display/drivers/intel-display/dpll.cc

display::ScopedValueChange<int> OverridePowerOnWaitTimeoutMsForTesting (int timeout_ms)

static

Defined at line 541 of file ../../src/graphics/display/drivers/intel-display/dpll.cc

bool DoEnable (const DdiPllConfig & pll_config)

DisplayPll overrides:

Defined at line 466 of file ../../src/graphics/display/drivers/intel-display/dpll.cc

bool DoDisable ()

Defined at line 528 of file ../../src/graphics/display/drivers/intel-display/dpll.cc