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Source - ArchitecturalFeatureTrapRegisterNoVhe
- The layout of [
CPTR_EL2] and [CPTR_EL3] when HCR_EL2.E2H == 0. - ArchitecturalFeatureTrapRegisterVhe
- The layout of [
CPTR_EL2] and [CPTR_EL3] when HCR_EL2.E2H == 1 (FEAT_VHE). - BreakpointControlRegister
- The layout of
DBGBCR<n>_EL1. - CacheLevelIdRegister
- The layout of
CLIDR_EL1. - CacheSizeIdRegister
- The layout of
CCSIDR_EL1. - CacheSizeIdRegisterCcidx
- The layout of
CCSIDR_EL1_CCIDX. - CacheSizeSelectionRegister
- The layout of
CSSELR_EL1. - CacheTypeRegister
- The layout of
CTR_EL0. - CounterTimerHypervisorControlRegisterNoVhe
- The layout of [
CNTHCTL_EL2] when HCR_EL2.E2H == 0. - CounterTimerHypervisorControlRegisterVhe
- The layout of [
CNTHCTL_EL2] when HCR_EL2.E2H == 1 (FEAT_VHE). - CurrentEl
- The layout of
CURRENT_EL. - Daif
- The layout of
DAIF. - DataCacheZeroIdRegister
- The layout of
DCZID_EL0. - ExceptionLinkRegister
- The layout of
ELR_EL1, ELR_EL2, and ELR_EL3. - ExceptionSyndromeRegister
- The layout of
ESR_EL1, ESR_EL2, and ESR_EL3. - ExtendedHypervisorConfigurationRegister
- The layout of
HCRX_EL2. - ExtendedTranslationControlRegister
- The layout of
TCR2_EL1. - HypervisorConfigurationRegister
- The layout of
HCR_EL2. - InstructionSetAttributeRegister0
- The layout of
ID_AA64ISAR0_EL1. - InstructionSetAttributeRegister1
- The layout of
ID_AA64ISAR1_EL1. - InstructionSetAttributeRegister2
- The layout of
ID_AA64ISAR2_EL1. - InterruptControllerSystemRegisterEnableRegister
- The layout of
ICC_SRE_EL1, ICC_SRE_EL2, and ICC_SRE_EL3. - MemoryAttrIndirectionRegister
- The layout of
MAIR_EL1 and MAIR_EL2. - MemoryModelFeatureRegister0
- The layout of
ID_AA64MMFR0_EL1. - MemoryModelFeatureRegister1
- The layout of
ID_AA64MMFR1_EL1. - MemoryModelFeatureRegister2
- The layout of
ID_AA64MMFR2_EL1. - MemoryModelFeatureRegister3
- The layout of
ID_AA64MMFR3_EL1. - MemoryModelFeatureRegister4
- The layout of
ID_AA64MMFR4_EL1. - MultiprocessorAffinityRegister
- The layout of
MPIDR_EL1 and VMPIDR_EL2. - Nzcv
- The layout of
NZCV. - ProcessorFeatureRegister0
- The layout of
ID_AA64PFR0_EL1. - ProcessorFeatureRegister1
- The layout of
ID_AA64PFR1_EL1. - SavedProgramStatusRegister
- The layout of
SPSR_EL1, SPSR_EL2, and SPSR_EL3. - SecureConfigurationRegister
- The layout of
SCR_EL3. - StackPointerRegister
- The layout of
SP_EL1, SP_EL2, and [SP_EL3]. - SystemControlRegister2El1
- The layout of
SCTLR2_EL1. - SystemControlRegister2El2
- The layout of
SCTLR2_EL2. - SystemControlRegister2El3
- The layout of
SCTLR2_EL3. - SystemControlRegisterEl1
- The layout of
SCTLR_EL1. - SystemControlRegisterEl2
- The layout of
SCTLR_EL2. - SystemControlRegisterEl3
- The layout of
SCTLR_EL3. - TranslationControlRegisterEl1
- The layout of
TCR_EL1. - TranslationControlRegisterEl2
- The layout of
TCR_EL2. - TranslationTableBaseRegister
- The layout of
TTBR0_EL1, TTBR0_EL2, TTBR0_EL3,
TTBR1_EL1, TTBR1_EL2, [TTBR1_EL3], and VTTBR_EL2. - VectorBaseAddressRegister
- The layout of
VBAR_EL1, VBAR_EL2, and VBAR_EL3. - VirtualizationTranslationControlRegister
- The layout of
VTCR_EL2. - WatchpointControlRegister
- The layout of
DBGWCR<n>_EL1.
- AsidSize
- ASID size.
- CacheType
- The type of cache implemented at a given level, per the
ctype<n> fields
of CacheLevelIdRegister. - CacheabilityAttribute
- The cacheability attribute of a normal memory regions, as defined by the
TCR_ELx.IRGNn and TCR_ELx.ORGNn fields.
- ExceptionClass
- Some values are only possible in ESR_EL2 and/or ESR_EL3.
- IdAa64IsaR0Aes
- IdAa64IsaR0Atomic
- IdAa64IsaR0Crc32
- IdAa64IsaR0DotProd
- IdAa64IsaR0Fhm
- IdAa64IsaR0Rdm
- IdAa64IsaR0Rndr
- IdAa64IsaR0Sha1
- IdAa64IsaR0Sha2
- IdAa64IsaR0Sha3
- IdAa64IsaR0Sm3
- IdAa64IsaR0Sm4
- IdAa64IsaR0Tlb
- IdAa64IsaR0Ts
- IdAa64IsaR1Bf16
- IdAa64IsaR1Dgh
- IdAa64IsaR1Dpb
- IdAa64IsaR1Fcma
- IdAa64IsaR1Frintts
- IdAa64IsaR1Gpa
- IdAa64IsaR1Gpi
- IdAa64IsaR1I8mm
- IdAa64IsaR1Jscvt
- IdAa64IsaR1Lrcpc
- IdAa64IsaR1Ls64
- IdAa64IsaR1Pauth
- IdAa64IsaR1Sb
- IdAa64IsaR1Specres
- IdAa64IsaR1Xs
- IdAa64IsaR2Apa3
- IdAa64IsaR2Ats1a
- IdAa64IsaR2Bc
- IdAa64IsaR2Clrbhb
- IdAa64IsaR2Cssc
- IdAa64IsaR2Gpa3
- IdAa64IsaR2Lut
- IdAa64IsaR2Mops
- IdAa64IsaR2PacFrac
- IdAa64IsaR2Prfmslc
- IdAa64IsaR2Rpres
- IdAa64IsaR2Rprfm
- IdAa64IsaR2Sysinstr128
- IdAa64IsaR2Sysreg128
- IdAa64IsaR2Wfxt
- IdAa64Pfr0Amu
- IdAa64Pfr0Csv2
- IdAa64Pfr0Csv3
- IdAa64Pfr0Dit
- IdAa64Pfr0El
- IdAa64Pfr0Fp
- IdAa64Pfr0Gic
- IdAa64Pfr0Mpam
- IdAa64Pfr0Ras
- IdAa64Pfr0Sel2
- IdAa64Pfr0Sve
- IdAa64Pfr1El1Bt
- IdAa64Pfr1El1Csv2Frac
- IdAa64Pfr1El1Df2
- IdAa64Pfr1El1Gcs
- IdAa64Pfr1El1Mte
- IdAa64Pfr1El1MteFrac
- IdAa64Pfr1El1Mtex
- IdAa64Pfr1El1Nmi
- IdAa64Pfr1El1Pfar
- IdAa64Pfr1El1RndrTrap
- IdAa64Pfr1El1Sme
- IdAa64Pfr1El1Ssbs
- IdAa64Pfr1El1The
- L1ICachePolicy
- L1 instruction cache policy.
- PhysicalAddressSize
- Physical address size.
- ShareabilityAttribute
- The cache shareability attribute for memory regions, as defined by the
TCR_ELx.SHn fields.
- SpsrExceptionLevel
- TagCacheType
- The type of allocation tag cache implemented at a given level, per the
ttype<n> fields of CacheLevelIdRegister (FEAT_MTE2). - TagCheckFault
- TcrTg0Value
- Granule size values for the TCR_EL1 and TCR_EL2 fields.
- TcrTg1Value
- Granule size values for the TCR_EL1.TG1 field.
- CCSIDR_EL1
- [arm/sysreg]/ccsidr_el1: CCSIDR_EL1, Current Cache Size ID Register
- CCSIDR_EL1_CCIDX
- [arm/sysreg]/ccsidr_el1: CCSIDR_EL1, Current Cache Size ID Register
- CLIDR_EL1
- [arm/sysreg]/clidr_el1: CLIDR_EL1, Cache Level ID Register
- CNTHCTL_EL2_NO_VHE
- [arm/sysreg]/cnthctl_el2: Counter-timer Hypervisor Control register (EL2) when
HCR_EL2.E2H == 0 - CNTHCTL_EL2_VHE
- [arm/sysreg]/cnthctl_el2: Counter-timer Hypervisor Control register (EL2) when
HCR_EL2.E2H == 1 (FEAT_VHE) - CPTR_EL2_NO_VHE
- [arm/sysreg]/cptr_el2: Architectural Feature Trap Register (EL2) when
HCR_EL2.E2H == 0 - CPTR_EL2_VHE
- [arm/sysreg]/cptr_el2: Architectural Feature Trap Register (EL2) when
HCR_EL2.E2H == 1 (FEAT_VHE) - CPTR_EL3_NO_VHE
- [arm/sysreg]/cptr_el3: Architectural Feature Trap Register (EL3) when
HCR_EL2.E2H == 0 - CPTR_EL3_VHE
- [arm/sysreg]/cptr_el3: Architectural Feature Trap Register (EL3) when
HCR_EL2.E2H == 1 (FEAT_VHE) - CSSELR_EL1
- [arm/sysreg]/csselr_el1: CSSELR_EL1, Cache Size Selection Register
- CTR_EL0
- [arm/v8]: D13.2.33 CTR_EL0, Cache Type Register.
- CURRENT_EL
- [arm/sysreg]/currentel: CurrentEL, Current Exception Level
- DAIF
- [arm/sysreg]/currentel: DAIF, Interrupt Mask Bits
- DBGBCR0_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR1_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR2_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR3_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR4_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR5_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR6_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR7_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR8_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR9_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR10_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR11_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR12_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR13_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR14_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBCR15_EL1
- [arm/sysreg]/dbgbcrn_el1: DBGBCR_EL1, Debug Breakpoint Control Registers
- DBGBVR0_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR1_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR2_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR3_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR4_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR5_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR6_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR7_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR8_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR9_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR10_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR11_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR12_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR13_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR14_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGBVR15_EL1
- [arm/sysreg]/dbgbvrn_el1: DBGBVR_EL1, Debug Breakpoint Value Registers
- DBGWCR0_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR1_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR2_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR3_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR4_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR5_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR6_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR7_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR8_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR9_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR10_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR11_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR12_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR13_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR14_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWCR15_EL1
- [arm/sysreg]/dbgwcrn_el1: DBGWCR_EL1, Debug Watchpoint Control Registers
- DBGWVR0_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR1_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR2_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR3_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR4_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR5_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR6_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR7_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR8_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR9_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR10_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR11_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR12_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR13_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR14_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DBGWVR15_EL1
- [arm/sysreg]/dbgwvrn_el1: DBGWVR_EL1, Debug Watchpoint Value Registers
- DCZID_EL0
- [arm/v8]: D13.2.36 DCZID_EL0, Data Cache Zero ID register
- DEBUG_BANK_SIZE
- The number of registers in each of the
DBGB{C,V}R<n>_EL1 and
DBGW{C,V}R<n>_EL1 banks; the count actually implemented is reported by
ID_AA64DFR0_EL1. - ELR_EL1
- [arm/sysreg]/elr_el1: Exception Link Register (EL1)
- ELR_EL2
- [arm/sysreg]/elr_el2: Exception Link Register (EL2)
- ELR_EL3
- [arm/sysreg]/elr_el3: Exception Link Register (EL3)
- ESR_EL1
- [arm/sysreg]/esr_el1: Exception Syndrome Register (El1)
- ESR_EL2
- [arm/sysreg]/esr_el2: Exception Syndrome Register (El2)
- ESR_EL3
- [arm/sysreg]/esr_el3: Exception Syndrome Register (El3)
- HCRX_EL2
- [arm/sysreg]/hcrx_el2: Extended Hypervisor Configuration register (EL2)
- HCR_EL2
- [arm/sysreg]/hcr_el2: Hypervisor Configuration register (EL2)
- ICC_SRE_EL1
- [arm/sysreg]/icc_sre_el1: Interrupt Controller System Register Enable Register (EL1)
- ICC_SRE_EL2
- [arm/sysreg]/icc_sre_el2: Interrupt Controller System Register Enable Register (EL2)
- ICC_SRE_EL3
- [arm/sysreg]/icc_sre_el3: Interrupt Controller System Register Enable Register (EL3)
- ID_AA64ISAR0_EL1
- [arm/sysreg]/ID_AA64ISAR0_EL1: AArch64 Instruction Set Attribute Register 0
- ID_AA64ISAR1_EL1
- [arm/sysreg]/ID_AA64ISAR1_EL1: AArch64 Instruction Set Attribute Register 1
- ID_AA64ISAR2_EL1
- [arm/sysreg]/ID_AA64ISAR2_EL1: AArch64 Instruction Set Attribute Register 2
- ID_AA64MMFR0_EL1
- [arm/v9]: D24.2.82 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0
- ID_AA64MMFR1_EL1
- [arm/v9]: D24.2.83 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1
- ID_AA64MMFR2_EL1
- [arm/v9]: D24.2.84 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2
- ID_AA64MMFR3_EL1
- [arm/v9]: D24.2.85 ID_AA64MMFR3_EL1, AArch64 Memory Model Feature Register 3
- ID_AA64MMFR4_EL1
- [arm/v9]: D24.2.86 ID_AA64MMFR4_EL1, AArch64 Memory Model Feature Register 4
- ID_AA64PFR0_EL1
- [arm/sysreg]/ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
- ID_AA64PFR1_EL1
- [arm/sysreg]/ID_AA64PFR1_EL1: AArch64 Processor Feature Register 1
- MAIR_EL1
- [arm/v8]: D13.2.95 MAIR_EL1, Memory Attribute Indirection Register, EL1
- MAIR_EL2
- [arm/v8]: D13.2.96 MAIR_EL2, Memory Attribute Indirection Register, EL2
- MPIDR_EL1
- [arm/sysreg]/mpidr_el1: Multiprocessor Affinity Register (EL1)
- NZCV
- [arm/sysreg]/nzcv: Condition Flags
- SCR_EL3
- [arm/sysreg]/scr_el3: Secure Configuration Register
- SCTLR2_EL1
- [arm/sysreg]/sctlr2_el1: System Control Register 2 (EL1)
- SCTLR2_EL2
- [arm/sysreg]/sctlr2_el2: System Control Register 2 (EL2)
- SCTLR2_EL3
- [arm/sysreg]/sctlr2_el3: System Control Register 2 (EL3)
- SCTLR_EL1
- [arm/sysreg]/sctlr_el1: System Control Register (EL1)
- SCTLR_EL2
- [arm/sysreg]/sctlr_el2: System Control Register (EL2)
- SCTLR_EL3
- [arm/sysreg]/sctlr_el3: System Control Register (EL3)
- SPSR_EL1
- [arm/sysreg]/spsr_el1: Saved Program Status Register (El1)
- SPSR_EL2
- [arm/sysreg]/spsr_el2: Saved Program Status Register (El2)
- SPSR_EL3
- [arm/sysreg]/spsr_el3: Saved Program Status Register (El3)
- SP_EL0
- [arm/sysreg]/sp_el0: Stack Pointer (EL0)
- SP_EL1
- [arm/sysreg]/sp_el1: Stack Pointer (EL1)
- SP_EL2
- [arm/sysreg]/sp_el2: Stack Pointer (EL2)
- TCR2_EL1
- [arm/v9]: D23.2.172 TCR2_EL1, Translation Control Register (EL1)
- TCR_EL1
- [arm/v8]: D13.2.120 TCR_EL1, Translation Control Register (EL1)
- TCR_EL2
- [arm/v8]: D13.2.121 TCR_EL2, Translation Control Register (EL2)
- TTBR0_EL1
- [arm/v8]: D13.2.132 TTBR0_EL1, Translation Table Base Register 0 (EL1)
- TTBR0_EL2
- [arm/v8]: D13.2.133 TTBR0_EL2, Translation Table Base Register 0 (EL2)
- TTBR0_EL3
- [arm/v8]: D13.2.134 TTBR0_EL3, Translation Table Base Register 0 (EL3)
- TTBR1_EL1
- [arm/v8]: D13.2.135 TTBR1_EL1, Translation Table Base Register 1 (EL1)
- TTBR1_EL2
- [arm/v8]: D13.2.136 TTBR1_EL2, Translation Table Base Register 1 (EL2)
- VBAR_EL1
- [arm/sysreg]/vbar_el1: Vector Base Address Register (EL1)
- VBAR_EL2
- [arm/sysreg]/vbar_el2: Vector Base Address Register (EL2)
- VBAR_EL3
- [arm/sysreg]/vbar_el3: Vector Base Address Register (EL3)
- VTCR_EL2
- [arm/v8]: VTCR_EL2, Virtualization Translation Control Register
- VTTBR_EL2
- [arm/v8]: VTTBR_EL2, Virtualization Translation Table Base Register (EL2)