class SimSmmuHardwareModel

Defined at line 126 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

SimSmmuHardwareModel models an ARM SMMUv2 controller (IHI 0062) paired with:

1. Non-coherent table walks reading strictly from PmmMock's PoC DRAM view

(poc_dram_priv), catching any missing or partial CleanDataCacheRange.

2. An infinite-capacity, multi-version Page Walk Cache (PWC, L0..L2) and

IOTLB (L3) that retains all valid descriptor versions ever loaded until

an explicit invalidation (TLBIVA / TLBIASID / TLBIALLNSNH) followed by

synchronization (TLBSYNC / TLBGSYNC).

3. Eager speculative walking of poc_dram_view on every CleanDataCacheRange,

every TTBR0/TCR/SCTLR enable, and every TLBSYNC / TLBGSYNC.

4. Immediate detection of Make-Before-Break violations, Hardware-Writable

PTE hazards (requiring AF == 1

DBM == 0 on all valid L3 PTEs and

TCR2.HA == 0

TCR2.HD == 0), and premature page-table page frees to PMM

before TLBSYNC.

Public Methods

void SimSmmuHardwareModel ()

Defined at line 173 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void SimSmmuHardwareModel (const Config & cfg)

Defined at line 174 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void ~SimSmmuHardwareModel ()

Defined at line 176 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void Reset ()

Defined at line 178 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void Detach ()

Defined at line 248 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

zbi_dcfg_arm_smmu_driver_t MakeZbiConfig (const std::vector<uint32_t> & handoff_smrs, uint32_t num_cb_override, uint32_t num_smr_override)

Defined at line 253 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

const Config & config ()

Defined at line 279 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint32_t SidMask ()

The mask of implemented stream ID bits (IDR0.NUMSIDB of them).

Defined at line 281 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

bool has_hazard ()

Defined at line 282 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

const std::vector<std::string> & hazards ()

Defined at line 283 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void ClearHazards ()

Defined at line 284 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void set_assert_on_hazard (bool v)

Defined at line 285 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

size_t clean_dcache_call_count ()

Defined at line 286 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

size_t tlb_sync_call_count ()

Defined at line 287 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

size_t tlb_gsync_call_count ()

Defined at line 288 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

size_t descriptor_write_count ()

The number of descriptor stores observed in translation tables. A zero-fill

of a table counts once for each descriptor it clears.

Defined at line 291 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void PreconfigureBootloaderSmrg (uint32_t smrg_ndx, uint16_t stream_id, uint16_t mask, S2CR_Type type, uint32_t cb_ndx, CBAR_Type cbar_type, bool sctlr_m, bool epd0, bool epd1)

Pre-configure a bootloader SMRG and optional Context Bank prior to Smmu::Create

to test AdoptSmrg in Passthru and Enforced modes.

Defined at line 295 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

ServicedInterrupts ServicePendingInterrupts ()

Runs the driver's handler for every fault interrupt which is asserted,

enabled and unmasked, and reports which ones ran.

Fault interrupts are level-sensitive: one stays asserted for as long as its

status register is non-zero. A fault recorded while the interrupt was

disabled or masked is therefore delivered later, as soon as the driver

enables and unmasks it again. Tests call this after a driver operation,

which is when such a deferred interrupt would reach the CPU. (It cannot be

called from inside a register write: the driver may hold the locks its

handler takes.)

Defined at line 340 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

bool InjectGlobalFaultIrq (uint32_t gfsr, uint64_t gfar, uint32_t gfsynr0, uint16_t stream_id)

Records a global fault with a syndrome chosen by the test, then delivers

the global fault interrupt if the driver has it enabled and unmasked.

Returns true if the handler ran.

Defined at line 371 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

bool InjectContextFaultIrq (uint32_t cb_ndx, uint32_t fsr, uint64_t far, uint32_t fsynr0, uint16_t stream_id)

Records a context fault on |cb_ndx| with a syndrome chosen by the test,

then delivers every fault interrupt the driver has enabled and unmasked.

Returns true if |cb_ndx|'s handler ran.

Defined at line 379 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

DmaTranslationResult DeviceAccess (uint16_t stream_id, uint64_t iova, uint32_t access_perms, ServicedInterrupts * out_serviced)

Simulates one access by a device: translates it and, if the access faults,

records the fault as the hardware would and delivers the fault interrupt if

the driver has it enabled and unmasked. Unlike the Inject*() operations,

the reported syndrome is whatever the hardware rules produce for this

access, not values chosen by the test.

Defined at line 391 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint32_t gfsr ()

Defined at line 445 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint32_t cb_fsr (uint32_t cb_ndx)

Defined at line 446 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint32_t cb_sctlr (uint32_t cb_ndx)

Defined at line 447 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint32_t smr (uint32_t smrg_ndx)

Defined at line 448 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint32_t s2cr (uint32_t smrg_ndx)

Defined at line 449 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

bool VerifyQuiescent ()

Checks the invariants that must hold whenever no driver operation is in

progress, recording a hazard for each violation. Returns true if no hazard

is recorded (now or earlier).

1. No TLB invalidation is posted but not yet synced.

2. Every cached PWC/IOTLB descriptor is still what a fresh walk of PoC DRAM

from an enabled context with that ASID would read. Anything else is a

stale entry: the driver changed or removed a translation and returned

without completing its invalidation.

Without this, a missing invalidation is only noticed if a later step

happens to reuse or probe the same input address.

Defined at line 463 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

std::optional<uint32_t> FindContextBankForStreamId (uint16_t stream_id)

Find which Context Bank currently serves a given StreamID (if any).

Defined at line 529 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

DmaTranslationResult TranslateDma (uint16_t stream_id, uint64_t iova, uint32_t access_perms)

Translate a simulated DMA transaction from |stream_id| at |iova| with

requested |access_perms| (IOMMU_FLAG_PERM_READ / WRITE / EXECUTE), walking

strictly the PoC DRAM view and checking the multi-version IOTLB/PWC.

Defined at line 552 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint32_t Read32 (uint64_t offset)

FakeMmioHandler implementation

Defined at line 791 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void Write32 (uint64_t offset, uint32_t val)

Defined at line 812 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

uint64_t Read64 (uint64_t offset)

Defined at line 835 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h

void Write64 (uint64_t offset, uint64_t val)

Defined at line 857 of file ../../zircon/kernel/dev/iommu/arm_smmu/tests/sim_smmu_hardware_model.h