arm_smmu

Namespaces

Enumerations

enum class ArmSmmuMode
Name Value
kDisabled 0
kPassthru 1
kEnforced 2

See kernel.arm-smmu-mode

Defined at line 13 of file ../../zircon/kernel/dev/iommu/arm_smmu/include/dev/arm_smmu/constants.h

enum class AddrMode
Name Value Comments
k32Bit 0

AArch32 Short-descriptor
kExt32Bit 1

AArch32 Long-descriptor
k64Bit 2

AArch64
kInvalid 3 --

The addressing mode for a context bank determined using values in CBA2R and TCR.

Defined at line 20 of file ../../zircon/kernel/dev/iommu/arm_smmu/include/dev/arm_smmu/constants.h

enum class BtiMode
Name Value Comments
kFault 0

Fault mode : A fault has occurred. Either a PMT has been leaked, or the HW
attempted to access something it didn't have access to and we
noticed. Access is restricted until user-mode takes control of
their HW and signals that it has by calling
`zx_bti_release_quarantine`.
kBypass 1

Passthru mode: No translation is performed, all accesses are allowed.
kTranslation 2

Enforced mode: Translation is performed, only pinned memory can be accessed.
kAdopted 3

Adopted mode : The configuration is whatever was passed to us by our bootloader.
kShutdown 4

Shutdown : The BTI has been shutdown. HW should be in Fault mode, but
cannot ever return to an operational mode. The BTI is about to
be destroyed.
kInvalid 5 --

Operational mode for a SmmuBti.

This enum is used in two places, at the BTI level, and at the context bank level for the (single)

context bank owned by a BTI. Note that when operating in fully enforced mode, the BTI may be in

the Fault state (preventing new pin operations) while its ContextBank remains in Translation mode

in order to continue to allow access to actively pinned PMTs, while specifically denying access

to leaked PMT regions.

In the context of a Context bank, the values used in this enum are not specific to any one

register value. Instead, they reflect the way that we choose to model the three modes of

operation using the CBAR (gr1), SCTLR (cb(N)), and TCR (cb(N)) registers.

Their definitions for each mode are as follows.

Mode | CBAR.TYPE | SCTLR.M | TCR.EPD0 | TCR.EPD1 | Notes

------------+-------------+---------+----------+----------+-------------------------------------

Translation | S1TS2Bypass | 1 | 0 | 1 | MMU enabled, TTBR0 enabled

Bypass | S1TS2Bypass | 0 | 1 | 1 | MMU + TTBRs Disabled

Fault | S1TS2Bypass | 1 | 0 | 0 | MMU enabled, TTBRs disabled

Adopted | ??? | ??? | ??? | ??? | Register config at time of adoption.

Shutdown | S1TS2Bypass | 1 | 0 | 0 | Same as fault, deny all access.

Note that all of the modes (except adopted) use Stage 1 Translate, Stage 2 Bypass as their

CBAR type. Stage 2's configuration is frequently under the control of either the hypervisor or

the secure monitor, which may deny any attempt to put the system into a S1TS2Fault mode in order

to force faulting. Additionally, while we might specify either S2Bypass or S2Translate, we

typically have no control over Stage 2 behavior from EL1. We configure for S2Bypass, assuming

that there is no S2 translation going on, however it may be the case that the system chooses to

either change our written value to S1TS2Translate if it wants to perform translation, or to lie

to us by reporting that our CBAR.TYPE is S1TS2Bypass even though (under the hood) it has actually

configured for Stage 2 Translation.

Either way, we are still able to represent all three of the primary modes with S1TS2Bypass. For

full translation, we enable the MMU, and TTBR0 which is configured to point to our page tables.

TTBR1 is not currently used in any mode. For bypass mode, we disable the MMU, which means that

all transactions which reach this context bank are simply accepted and passed through as is with

no translation. Finally, when configured for Fault/Shutdown, the MMU is enabled, but both TTBRs

are disabled, meaning there are no valid/active translation table entries, ensuring that

"translation" in Fault mode always fails.

Defined at line 67 of file ../../zircon/kernel/dev/iommu/arm_smmu/include/dev/arm_smmu/constants.h

Records

Functions

  • ktl::optional<ArmSmmuMode> GetSmmuMode (const char * mode_string, ktl::optional<uint64_t> base_addr)

    Determines the proper ArmSmmuMode if specified, or simply returns the default

    mode otherwise.

    Which mode to choose is determined by the "mode_string". It is

    a string with the following form, given in a pseudo-regular expression

    notation:

    <mode

    >(,

    <base

    _addr>=

    <mode

    >)*

    "<mode>" is one of three tokens, "disabled", "passthru" or "enforced",

    corresponding to each of the three defined ArmSmmuModes. The first mode

    listed is mandatory and specifies the default operating mode. This is

    followed by a comma separated list of zero or more modes for specific SMMU

    instances in the form "<base_addr>=<mode>". "<base_addr>" is a 64-bit

    unsigned identifying a specific instance of an SMMU for which the given mode

    should be used.

    When GetSmmuMode is called, a `base_addr` may optionally be passed. When no

    base address is provided, GetSmmuMode should return the default operating

    mode. When a base address is passed, GetSmmuMode should return the mode for

    the first optional entry which matches that base address. If no entry is

    found which matches the base address, the default mode should be returned

    instead. If a chosen mode token string is invalid, a warning should be

    printed, and the value ArmSmmuMode::kDisabled should be returned instead.

    Defined at line 153 of file ../../zircon/kernel/dev/iommu/arm_smmu/smmu_mode.cc

  • bool ValidateSmmuModeString (const char * mode_string)

    Defined at line 157 of file ../../zircon/kernel/dev/iommu/arm_smmu/smmu_mode.cc