class HdmiClockTreeControl

Defined at line 1043 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

HHI_VID_PLL_CLK_DIV - Configures the "vid_pll_clk" clock signal.

The HDMI clock tree has a pattern repeater that can repeat a given (or

fixed) bit pattern, one bit at each clock cycle, which effectively acts as a

frequency divider of the input clock signal. This register controls the

behavior of the pattern generator.

A311D Datasheet, Section 8.7.1.3 "HDMI Clock Tree", Page 112-113; Section

8.7.6 Register Descriptions, Page 153.

S905D2 Datasheet, Section 6.6.2.3 "HDMI Clock Tree", Page 96-97; Section

6.6.6 Register Descriptions, Page 138-139.

S905D3 Datasheet, Section 6.7.2.3 "HDMI Clock Tree", Page 96-97; Section

6.7.6 Register Descriptions, Page 131.

Public Members

 field_RsvdZ_1048

 field_clock_output_enabled_1051

 field_bypass_pattern_generators_1060

 field_pattern_generator_mode_selection_1064

 field_preset_pattern_update_enabled_1068

 field_pattern_generator_state_1096

static const uint32_t[] kSupportedFrequencyDividerRatiosArray

static span kSupportedFrequencyDividerRatios

Public Methods

int PatternSize ()

The generated signal's period (cycle size), in bits.

Returns 0 if the pattern generator is bypassed.

Defined at line 13 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.cc

uint32_t Pattern ()

The pattern repeated by the pattern generator.

Returns 0 if the pattern generator is bypassed.

Defined at line 29 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.cc

HdmiClockTreeControl & SetFrequencyDividerRatio (uint32_t divider_ratio_u28_4)

Sets the pattern generator so that it works as a frequency divider with a

division ratio of `division_ratio_u28_4`.

`division_ratio_u28_4` is a U28.4 format fixed-point fraction with 28

integer bits and 4 fractional bits.

`division_ratio_u28_4` must be one of the values in

`kSupportedFrequencyDividerRatios`.

Defined at line 46 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.cc

hwreg::RegisterAddr<HdmiClockTreeControl> Get ()

Defined at line 1045 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType clock_output_enabled ()

If false, the output clock vid_pll_clk is gated.

Defined at line 1051 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_clock_output_enabled (typename SelfType::ValueType val)

If false, the output clock vid_pll_clk is gated.

Defined at line 1051 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType bypass_pattern_generators ()

If true, the output clock matches the HDMI PLL clock.

When this bit is true, the pattern repeater configuration does not

influence the output signal.

`Pattern()`, `PatternSize()` and `SetFrequencyDividerRatio()` helpers are

preferred over direct field manipulations.

Defined at line 1060 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_bypass_pattern_generators (typename SelfType::ValueType val)

If true, the output clock matches the HDMI PLL clock.

When this bit is true, the pattern repeater configuration does not

influence the output signal.

`Pattern()`, `PatternSize()` and `SetFrequencyDividerRatio()` helpers are

preferred over direct field manipulations.

Defined at line 1060 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

HdmiClockTreePatternGeneratorModeSource pattern_generator_mode_selection ()

`Pattern()`, `PatternSize()` and `SetFrequencyDividerRatio()` helpers are

preferred over direct field manipulations.

Defined at line 1064 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_pattern_generator_mode_selection (HdmiClockTreePatternGeneratorModeSource val)

`Pattern()`, `PatternSize()` and `SetFrequencyDividerRatio()` helpers are

preferred over direct field manipulations.

Defined at line 1064 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType preset_pattern_update_enabled ()

If false, the `preset_pattern` field is ignored when the register is

written.

Defined at line 1068 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_preset_pattern_update_enabled (typename SelfType::ValueType val)

If false, the `preset_pattern` field is ignored when the register is

written.

Defined at line 1068 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType pattern_generator_state ()

The bits output by the pattern generator, when not in fixed pattern mode.

For example, to get a clock signal at 1/5 of the HDMI PLL frequency (with a

60/40 duty cycle), use 15-bit repeater (source 2) and set the pattern to

0b111'00'111'00'111'00 to generate the following pattern (assuming the bits

are emitted from the least significant bit to the most significant bit):

(output) 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1

1 ______ ______ ______

0 ____ ____ ____

The pattern must fulfill the following constraints:

- The pattern's least significant bit must be zero.

- If PatternSize() is non-zero, the bit `PatternSize() - 1` is the most

significant bit set. In testing, this means the pattern will be at least

PatternSize()` and less than `1

(PatternSize() + 1)`.

- The number of 1 -> 0 bit transitions (when reading from the most

significant bit to the least significant bit) in `Pattern()` equals

`PatternSize() / (divider_ratio - 1.0)` for divider ratios greater than

one.

- The maximum length of a consecutive sequence of ones or zeros will

differ by at most 1 from the minimum length of a consecutive sequence

of ones or zeros.

`Pattern()`, `PatternSize()` and `SetFrequencyDividerRatio()` helpers are

preferred over direct field manipulations.

Defined at line 1096 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_pattern_generator_state (typename SelfType::ValueType val)

The bits output by the pattern generator, when not in fixed pattern mode.

For example, to get a clock signal at 1/5 of the HDMI PLL frequency (with a

60/40 duty cycle), use 15-bit repeater (source 2) and set the pattern to

0b111'00'111'00'111'00 to generate the following pattern (assuming the bits

are emitted from the least significant bit to the most significant bit):

(output) 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1

1 ______ ______ ______

0 ____ ____ ____

The pattern must fulfill the following constraints:

- The pattern's least significant bit must be zero.

- If PatternSize() is non-zero, the bit `PatternSize() - 1` is the most

significant bit set. In testing, this means the pattern will be at least

PatternSize()` and less than `1

(PatternSize() + 1)`.

- The number of 1 -> 0 bit transitions (when reading from the most

significant bit to the least significant bit) in `Pattern()` equals

`PatternSize() / (divider_ratio - 1.0)` for divider ratios greater than

one.

- The maximum length of a consecutive sequence of ones or zeros will

differ by at most 1 from the minimum length of a consecutive sequence

of ones or zeros.

`Pattern()`, `PatternSize()` and `SetFrequencyDividerRatio()` helpers are

preferred over direct field manipulations.

Defined at line 1096 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h