struct
Defined at line 756 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h
If false, the "cts_ge2d_clk" signal is gated. "cts_ge2d_clk" takes
"cts_vapbclk" output as its clock source and has no frequency dividers.
This bit is named "enable" in A311D, S905D2 and S905D3 datasheet register
descriptions, but the "EE clock table" shows that it gates the
"cts_ge2d_clk" signal. Besides, A311D2 datasheet also documents it as
""cts_ge2d_clk" enable" in the register descriptions.
A311D2 Datasheet, Section 7.6.5 Register Descriptions, Page 200.
Public Members
Field field